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參數(shù)資料
| 型號(hào)： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 23/112頁(yè) |
| 文件大小： | 1496K |
| 代理商： | QSMRM |
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QSM
REFERENCE MANUAL
CONFIGURATION AND CONTROL
MOTOROLA
3-7
WARNING
Ignoring the FREEZE signal can cause unpredictable results in the
background mode operation of the QSM, because the CPU is unable
to service interrupt requests in this mode. If FRZ1 equals one when
the FREEZE line is asserted, the QSM comes to an orderly halt on a
transfer boundary as if HALT had been asserted. The output pins
continue to drive their last state. Once the FREEZE signal is negated,
the QSM module restarts automatically.
FRZ0 — Freeze0
Reserved for future enhancement.
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted
1 = Supervisor access
All registers in the QSM are placed in supervisor-only space. For any access from
within user mode, address acknowledge (AACK) is not returned and the bus cycle is
transferred externally.
0 = User access
Because the QSM contains a mix of supervisor and user registers, AACK returns for
accesses with either supervisor or user mode, and the bus cycle remains internal. If a
supervisor-only register is accessed in user mode, the module responds as if an ac-
cess had been made to an unimplemented register location.
SUPV defines the assignable QSM registers as either supervisor-only data space or
unrestricted data space.
Bits [6:4] — Not Implemented
IARB — Interrupt Arbitration Identification Number
Each module that generates interrupts, including the QSM, must have an IARB field.
The value in this field is used to arbitrate for the IMB when two or more modules gen-
erate simultaneous interrupts of the same priority level. No two modules can share the
same IARB value. The reset value of the IARB field is $0, which prevents the QSM
from arbitrating during an interrupt acknowledge cycle (IACK). The IARB field should
be initialized by system software to a value between $F (highest priority) and $1 (low-
est priority). Otherwise, any interrupts generated are identified by the CPU as spuri-
ous.
3.2.2 QSM Test Register (QTEST)
QTEST is used in testing the QSM. Accesses to QTEST must be made while the MCU
is in test mode. Test mode is for manufacturing use only. Applications should not use
this register or enter test mode.
QTEST
— QSM Test Register
$YFFC02
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
TSBD SYNC TQSM
TMM
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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