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參數(shù)資料
| 型號(hào)： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊(cè) |
| 文件頁數(shù)： | 44/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
4-16
QSPI SUBMODULE
QSM
REFERENCE MANUAL
The amount of the delay between transfers is programmable by the user via the DTL
field in SPCR1. The range may be set from 1 – 489 μs at 16.78 MHz.
DSCK — PCS to SCK Delay
1 = DSCKL field in SPCR1 specifies value of delay from PCS valid to SCK
0 = PCS valid to SCK transition is 1/2 SCK
4.4 Operating Modes and Flowcharts
The QSPI utilizes an 80-byte block of dual-access static RAM accessible by both the
QSPI and the CPU. Because of this dual access capability, up to two wait states may
be inserted into CPU access times if the QSPI is in operation.
The RAM is divided into three segments: 16 command control bytes, 16 transmit data
words of information to be transmitted, and 16 receive data words for data to be re-
ceived. Once the CPU has a) set up a queue of QSPI commands, b) written the trans-
mit data segment with information to be sent, and c) enabled the QSPI, the QSPI
operates independently of the CPU. The QSPI executes all of the commands in its
queue, sets a flag indicating completion, and then either interrupts the CPU or waits
for CPU intervention.
The QSPI operates on a queue data structure contained in the QSPI RAM. Control of
the queue is handled by three pointers: the new queue pointer (NEWQP), the complet-
ed queue pointer (CPTQP), and the end queue pointer (ENDQP). NEWQP, contained
in SPCR2, points to the first command in the queue to be executed by the QSPI.
CPTQP, contained in SPSR, points to the command last executed by the QSPI.
ENDQP, also contained in SPCR2, points to the last command in the queue to be ex-
ecuted by the QSPI, unless wraparound mode is enabled (WREN = 1).
At reset, NEWQP is initialized to $0, causing QSPI execution to begin at queue ad-
dress $0 when the QSPI is enabled (SPE = 1). CPTQP is set by the QSPI to the queue
address ($0-$F) last executed, but is initialized to $0 at reset. ENDQP is also initialized
to $0 at reset, but should be changed by the user to reflect the last queue entry to be
transferred before enabling the QSPI. Leaving NEWQP and ENDQP set to $0 causes
a single transfer to occur when the QSPI is enabled.
The organization of the QSPI RAM requires that one byte of command control data,
one word of transmit data, and one word of receive data all correspond to one queue
entry, $0-$F.
After executing the current command, ENDQP is checked against CPTQP for an end-
of-queue condition. If a match occurs, the SPIF flag is set and the QSPI stops unless
wraparound mode is enabled.
The QSPI operates in one of two modes: master or slave. Master mode is used when
the MCU originates all data transfers. Slave mode is used when another MCU or a pe-
ripheral to the MCU initiates all serial transfers to the MCU via the QSPI. Switching be-
tween the two operating modes is achieved under software control by writing to the
master (MSTR) bit in SPCR0.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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