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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 86/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
A-8
USING THE QSPI FOR ANALOG DATA AQUISITION
For More Information On This Product,
Go to: www.freescale.com
QSM
REFERENCE MANUAL
rent drain will cause IR voltage drop in the traces. If an active IC is being powered by
the same trace, the switching current transients can cause enormous errors.
As the timing diagram shows, the MC145050 requires valid data on the DIN pin during
the rising edge of SCK. The data is allowed to change on the falling edge of SCK. This
determines the clock polarity and phase values that need to be programmed into the
QSPI (CPOL = 0, CPHA = 0).
Figure A-8 MC14050 Conversion and Transfer Timing
A.5 Timing Considerations
One factor determining overall system speed is the source impedance of the signal be-
ing measured. The impedance limits the maximum SCK clock frequency because the
SCK frequency is what determines the actual sample interval. For more information on
source impedance effect on clock frequency, refer to
Reference 4.
A source imped-
ance of less than 1000 ohms is assumed so that sample interval is not a constraint.
Calculate the maximum SCK frequency according to the following procedures. Ac-
cording to
Reference 4.
, the minimum SCLK pulse high and low widths (t
wh
, t
wl
) are
both 190 ns, the maximum propagation delay from SCK to DOUT (t
PHL
, t
PLH
) is 240
ns, and the minimum setup time from DIN to SCK (t
su
.A/D) is 100 ns.
Assuming a QSPI minimum data setup time (t
su
.Q, MISO to SCK) of 10 ns, to meet
QSPI input data timing requirements, the minimum clock pulse width is the greater of
(t
PLH
+ t
su
.Q) or (t
PHL
+ t
su
.Q). This yields 250 ns.
SCK
DIN
DOUT
CS
VALID CHIP SELECT
SCK PERIOD (500 ns)
QSPI DATA SETUP TIME
MUX ADDRESS B
CONVERSION RESULT
2 A/D CLKS + 300 ns = 1.3 μs
(CS VALID TO DOUT DRIVEN)
MUX ADDRESS A CONVERSION RESULT
(FROM PREVIOUSLY SELECTED MUX
ADDRESS – NOT SHOWN)
1
2
3
4
5
6
7
8
9
10
1
2
3
4
B3
B2
B1
B0
C3
C2
C1
C0
B9 (MSB)
B8
B7
B6
A9 (MSB)
A8
A7
A6
A5
A4
A3
A2
A1
A0
HI-Z
MUX
ADDRESS B
MUX
ADDRESS C
SAMPLE MUX ADDRESS B
HOLD + CONVERT B
(44 A/D CLKS)
22 μs
VALID CHIP SELECT
F
Freescale Semiconductor, Inc.
n
.
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