參數(shù)資料
型號(hào): QSMRM
英文描述: QSMRM QSM Queued Serial Module Reference Manual
中文描述: QSMRM QSM排隊(duì)串行模塊參考手冊(cè)
文件頁(yè)數(shù): 63/112頁(yè)
文件大?。?/td> 1496K
代理商: QSMRM
QSM
REFERENCE MANUAL
SCI SUBMODULE
MOTOROLA
5-7
in a previous data byte are not counted toward the 10 or 11 ones in an idle line. Hence,
the data content of the last byte transmitted does not affect the timing of idle-line de-
tection.
PT — Parity Type
1 = Odd parity
If the data contains an even number of ones, then the parity bit equals one. If the data
contains an odd number of ones, then the parity bit equals zero.
0 = Even parity
If the data contains an even number of ones, then the parity bit equals zero. If the data
contains an odd number of ones, then the parity bit equals one.
When parity is enabled, PT determines whether parity is even or odd for both the re-
ceiver and the transmitter.
PE — Parity Enable
1 = SCI parity enabled; the transmitter generates the parity bit and the receiver
checks incoming parity.
0 = SCI parity disabled
PE determines whether parity is enabled or disabled for both the receiver and the
transmitter. If PE is set, the transmitter internally generates the parity bit and appends
it to the data bits during transmission. The receiver checks the last bit before a stop bit
to determine if the correct parity was received. If the received parity bit is not correct,
the SCI sets the PF error flag in SCSR.
When PE is set, the most significant bit (MSB) of the data field is used for the parity
function, which results in either seven or eight bits of user data, depending on the con-
dition of M bit.
Table 5-3
lists the available choices.
M — Mode Select
1 = SCI frame: one start bit, nine data bits, one stop bit (eleven bits total)
0 = SCI frame: one start bit, eight data bits, one stop bit (ten bits total)
The M bit determines the SCI frame format. If M is clear (its reset value), the frame
format is one start bit, eight data bits, one stop bit. If M is set, the frame format is one
start bit, nine data bits, one stop bit.
The ninth data bit can be controlled by software to perform a function such as address
mark. Frames with the ninth data bit set could be identified as an address mark. All
receivers in a network could be placed in wakeup mode until an address mark is de-
tected, at which time all receivers would wake up and read the address. All receivers
being addressed could continue to receive the following message, while all receivers
not being addressed could be put back into wakeup mode.
Table 5-3 M and PE Bit Fields
M
0
0
1
1
PE
0
1
0
1
Result
8 Data Bits
7 Data Bits, 1 Parity Bit
9 Data Bits
8 Data Bits, 1 Parity Bit
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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