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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 52/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
4-24
QSPI SUBMODULE
QSM
REFERENCE MANUAL
Although the QSPI inherently supports multimaster operation, no special arbitration
mechanism is provided. The user is given a mode fault flag (MODF) to indicate a re-
quest for SPI master arbitration; however, the system software must implement the ar-
bitration. Note that unlike previous SPI systems, e.g., on the M68HC11 Family, MSTR
is not cleared by a mode fault being set nor are the QSPI pin output drivers disabled;
however, the QSPI is disabled when software clears SPE in QSPI register SPCR1.
Normally, the SPI bus performs simultaneous bidirectional synchronous transfers. The
serial clock on the SPI bus master supplies the clock signal (SCK) to time the transfer
of the bits. Four possible combinations of clock phase and polarity may be employed.
Data is transferred with the most significant bit first. The number of bits transferred per
command defaults to eight, but may be programmed to a value from 8–16 bits, using
the BITSE field.
Typically, outputs used for the SPI bus are not open-drain unless multiple SPI masters
are in the system. If needed, WOMQ in SPCR0 may be set to provide open-drain out-
puts. An external pull-up resistor should be used on each output bus line. WOMQ af-
fects all QSPI pins regardless of whether they are assigned to the QSPI or used as
general-purpose I/O.
4.4.1 Master Mode
When operated in master mode, the QSPI may initiate serial transfers. The QSPI is
unable to respond to any externally initiated serial transfers. QSM register DDRQS
should be written to direct the data flow on the QSPI pins used. The SCK pin should
be configured as an output. Pins MOSI and PCS3–PCS0/SS should be configured as
outputs as necessary. MISO should be configured as an input if necessary.
QSM register PQSPAR should be written to assign the necessary bits to the QSPI.
The pins necessary for master mode operation are MISO and/or MOSI, SCK, and one
or more of the PCS pins, depending on the number of external peripheral chips to be
selected. MISO is used as the data input pin in master mode, and MOSI is used as the
data output pin in master mode. Either or both may be necessary, depending on the
particular application. SCK is the serial clock output in master mode.
PCS[3:0]/SS are the select pins used to select external SPI peripheral chips for a serial
transfer initiated by the QSPI. These pins operate as either active-high or active-low
chip-selects. Other considerations for initialization are prescribed in
3.1 Overall QSM
Configuration Summary
.
4.4.1.1 Master Mode Operation
After reset, the QSM registers and the QSPI control registers must be initialized as de-
scribed above. In addition to the command control segment, the transmit data segment
may, depending upon the application, need to be initialized. If meaningful data is to be
sent out from the QSPI, the user should write the data to the transmit data segment
before enabling the QSPI.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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