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| 型號(hào)： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊 |
| 文件頁數(shù)： | 82/112頁 |
| 文件大小： | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
A-4
USING THE QSPI FOR ANALOG DATA AQUISITION
For More Information On This Product,
Go to: www.freescale.com
QSM
REFERENCE MANUAL
shows a breakdown of a single command control byte, and
Figure A-5
depicts a basic
QSPI master mode timing diagram. The control byte allows the programmer to cus-
tomize each serial transfer to the specific needs of the targeted peripheral. Chip-select
patterns are stored in the PCS[0:3] bit fields of each applicable control byte and are
driven onto the chip-select pins when the specified transfer begins. If set, the continue
(CONT) bit allows the QSPI to continue driving the programmed chip-select value until
the beginning of the next transfer. This procedure has the effect of concatenating mul-
tiple serial transfers to a single peripheral and allowing more than 16 bits per ex-
change. If the CONT bit is clear, a user-defined default value is driven onto the chip-
select pins between serial transfers.
Figure A-4 Command Control Byte
The PCS to SCK delay (DSCK) and delay after transfer (DT) bits enable user-defined
delays before and after the specified transfer. If DSCK is set, the first clock following
the chip-select assertion is delayed by a user-specified amount of time. Otherwise, the
first clock pulse is delayed one-half of an SCK period. This delay is necessary because
some peripherals require a relatively long period of time to respond.
Figure A-5 Basic QSPI Master Mode Timing Diagram
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0
COMMAND
CONTROL BITS
PERIPHERAL
CHIP-SELECT BITS
COMMAND CONTROL BYTE
MOSI
(TO
SLAVE)
MISO
(FROM
SLAVE)
Y = DELAY BETWEEN TRANSFERS
CLOCK RATE, POLARITY
DATA PHASE SHIFT
CHIP-SELECT PATTERN
PCS1
PCS0
SCK
Y
Y
Y
X
X
X
1
2
3
4
5
6
N
1
2
3
4
5
6
N
1
2
3
4
5
6
PROGRAMMABLE FEATURES:
N = NUMBER OF BITS
X = DELAY BEFORE FIRST CLOCK
F
Freescale Semiconductor, Inc.
n
.
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