參數(shù)資料
型號(hào)： QSMRM
英文描述： QSMRM QSM Queued Serial Module Reference Manual
中文描述： QSMRM QSM排隊(duì)串行模塊參考手冊(cè)
文件頁(yè)數(shù)： 58/112頁(yè)
文件大?。?/td> 1496K
代理商： QSMRM
MOTOROLA
5-2
SCI SUBMODULE
QSM
REFERENCE MANUAL
Even/Odd Parity Generation and Detection
— The user now has the choice either of seven or eight data bits plus one parity
bit, or of eight or nine data bits with no parity bit. Even or odd parity is available.
The transmitter automatically generates the parity bit for a transmitted byte.
The receiver detects when a parity error has occurred on a received byte and
sets a parity error flag.
QSM-Enhanced SCI Receiver Features:
Two Idle-Line Detect Modes
— Standard Motorola SCI systems detect an idle line when 10 or 11 consecutive
bit-times are all ones. Used with the receiver wakeup mode, the receiver can
be awakened prematurely if the message preceding the start of the idle line
contained ones in advance of its stop bit. The new (second) idle-line detect
mode starts counting idle time only after a valid stop bit is received, which en-
sures correct idle-line detection.
Receiver Active Flag (RAF)
— RAF indicates the status of the receiver. It is set when a possible start bit is
detected and is cleared when an idle line is detected. RAF is also cleared if the
start bit is determined to be line noise. This flag can be used to prevent colli-
sions in systems with multiple masters.
5.2 SCI Programmer's Model and Registers
The programmer's model (memory map) for the SCI submodule consists of the QSM
global and pin control registers (refer to
3.2 QSM Global Registers
and
3.3 QSM Pin
Control Registers
) and the four SCI registers. The SCI registers are listed in
Table
5-1
and consist of two control registers, one status register, and one data register. All
registers may be read or written at any time by the CPU. Rewriting the same value to
any SCI register does not disrupt operation; however, writing a different value into an
SCI register when the SCI is running may disrupt operation. To change register values,
the receiver and transmitter should be disabled with the transmitter allowed to finish
first. The status flags in register SCSR may be cleared at any time.
*Reads access the RDR; writes access the TDR.
When initializing the SC, the SCCR1 has two bits that should be written last; the trans-
mitter enable (TE) and receiver enable (RE) bits, which enable the SCI. Registers
SCCR0 and SCCR1 should both be initialized at the same time or before TE and RE
are asserted. A single word write to SCCR1 can be used to initialize the SCI and en-
able the transmitter and receiver.
Table 5-1 SCI Register
Address
$YFFC08
$YFFC0A
$YFFC0C
$YFFC0E
Name
SCCR0
SCCR1
SCSR
SCDR
Usage
SCI Control Register 0
SCI Control Register 1
SCI Status Register
SCI Data Register
Transmit Data Register (TDR)*
Receive Data Register (RDR)*
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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