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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 56/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
4-28
QSPI SUBMODULE
QSM
REFERENCE MANUAL
er value in CPTQP, increments the internal working queue pointer, and loads the new
transmit data from the transmit data segment into the data serializer. The internal
working queue pointer address is used the next time PCS0/SS is asserted, unless the
CPU writes to the NEWQP first.
The DT and DSCK command control bits are not used in slave mode. As a slave, the
QSPI does not drive the clock line nor the chip-select lines and, therefore, does not
generate a delay.
In slave mode, the QSPI shifts out the data in the transmit data segment. The transmit
data is loaded into the data serializer (refer to
Figure 5-9
) for transmission. When the
PCS0/SS pin is pulled low the MISO pin becomes active and the serializer then shifts
the 16 bits of data out in sequence, most significant bit first, as clocked by the incoming
SCK signal. The QSPI uses CPHA and CPOL to determine which incoming SCK edge
the MOSI pin uses to latch incoming data, and which edge the MISO pin uses to drive
the data out.
The QSPI transmits and receives data until reaching the end of the queue (defined as
a match with the address in ENDQP), regardless of whether PCS0/SS remains select-
ed or is toggled between serial transfers. Receiving the proper number of bits causes
the received data to be stored. The QSPI always transmits as many bits as it receives
at each queue address, until the BITS value is reached or PCS0/SS is negated.
4.4.2.2 Slave Wraparound Mode
When the QSPI reaches the end of the queue, it always sets the SPIF flag, whether
wraparound mode is enabled or disabled. An optional interrupt to the CPU is generat-
ed when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wrap-
around mode is enabled. A description of SPIFIE bit can be found in
4.3.3 QSPI
Control Register 2 (SPCR2)
.
In wraparound mode, the QSPI cycles through the queue continuously. Each time the
end of the queue is reached, the SPIF flag is set. If the CPU fails to clear SPIF, it re-
mains set, and the QSPI continues to send interrupt requests to the CPU (assuming
SPIFIE is set). The user may avoid causing CPU interrupts by clearing SPIFIE. As
SPIFIE is buffered, clearing it after the SPIF flag is asserted does not immediately stop
the CPU interrupts, but only prevents future interrupts from this source. To clear the
current interrupt, the CPU must read QSPI register SPSR with SPIF asserted, followed
by a write to SPSR with zero in SPIF (clear SPIF). Execution continues in wraparound
mode even while the QSPI is requesting interrupt service from the CPU. The internal
working queue pointer is incremented to the next address and the commands are ex-
received data located in the receive data segment.
Wraparound mode is properly exited in two ways: a) The CPU may disable wrap-
around mode by clearing WREN. The next time end of the queue is reached, the QSPI
sets SPIF, clears SPE, and stops; and, b) The CPU sets HALT. This second method
halts the QSPI after the current transfer is completed, allowing the CPU to negate
SPE. The CPU can immediately stop the QSPI by clearing SPE; however, this method
is not recommended, as it causes the QSPI to abort a serial transfer in process.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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