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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 40/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
4-12
QSPI SUBMODULE
QSM
REFERENCE MANUAL
MODF is asserted by the QSPI when the QSPI is the serial master (MSTR = 1) and
the slave select (PCS0/SS) input pin is pulled low by an external driver. This is possi-
ble only if the PCS0/SS pin is configured as input by DDRQS. This low input to SS is
not a normal operating condition. It indicates that a multimaster system conflict may
exist, that another MCU is requesting to become the SPI network master, or simply
that the hardware is incorrectly affecting PCS0/SS. SPE in SPCR1 is cleared, dis-
abling the QSPI. The QSPI pins revert to control by PORTQS. If MODF is set and
HMIE in SPCR3 is asserted, the QSPI generates an interrupt to the CPU.
The CPU may clear MODF by reading SPSR with MODF asserted, followed by writing
SPSR with a zero in MODF. After correcting the mode fault problem, the QSPI can be
re-enabled by asserting SPE.
The PCS0/SS pin may be configured as a general-purpose output instead of input to
the QSPI. This inhibits the mode fault checking function. In this case, MODF is not
used by the QSPI.
HALTA — Halt Acknowledge Flag
1 = QSPI halted
0 = QSPI not halted
HALTA is asserted by the QSPI when it has come to an orderly halt at the request of
the CPU, via the assertion of HALT. To prevent undefined operation, the user should
not modify any QSPI control registers or RAM while the QSPI is halted.
If HMIE in SPCR3 is set, the QSPI sends interrupt requests to the CPU when HALTA
is asserted. The CPU can only clear HALTA by reading SPSR with HALTA set and
then writing SPSR with a zero in HALTA.
Bit 4 — Not Implemented
CPTQP — Completed Queue Pointer
CPTQP contains the queue pointer value of the last command in the queue that was
completed. The value of CPTQP is not updated until the command has been complet-
ed entirely. While the first command in a queue is executing, CPTQP contains either
the reset value ($0) or the pointer to the last command completed in the previous
queue.
If the QSPI is halted, CPTQP may be used to determine which commands have not
been executed. The CPTQP may also be used to determine which locations in the re-
ceive data segment of the QSPI RAM contain valid received data.
4.3.6 QSPI RAM
The QSPI uses an 80-byte block of dual-access static RAM, which can be accessed
by both the QSPI and the CPU. Because of sharing, the length of time taken by the
CPU to access the QSPI RAM when the QSPI is enabled, may be longer than when
the QSPI is disabled. From one to four CPU wait states may be inserted by the QSPI
in the process of reading or writing.
The size and type of access of the QSPI RAM by the CPU affects the QSPI access
time. The QSPI is byte, word, and long-word addressable. Only word accesses of the
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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