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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊 |
| 文件頁數(shù)： | 53/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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QSM
REFERENCE MANUAL
QSPI SUBMODULE
MOTOROLA
4-25
Shortly after SPE is set, the QSPI commences operation at the address indicated by
NEWQP. The QSPI transmits the data found in the transmit data segment at the ad-
dress indicated by NEWQP, and the QSPI stores received data in the receive data
segment at the address indicated by NEWQP. Data is transferred synchronously with
the internally generated SCK.
Transmit data is loaded into the data serializer (refer to Figure 4-1). The QSPI employs
control bits, CPHA and CPOL, to determine which SCK edge the MISO pin uses to
latch incoming data and which edge the MOSI pin uses to start driving the outgoing
data. SPBR of SPCR0 determines the baud rate of SCK. DSCK DSCK and DSCKL
determine any peripheral chip-selects valid to SCK start delay.
The number of bits transferred is determined by BITSE and BITS fields. Two options
are available: the user may use the default value of 8 bits, or the user may program
the length from 8 – 16 bits, inclusive.
Once the proper number of bits are transferred, the QSPI stores the received data in
the receive data segment, stores the internal working queue pointer value in CPTQP,
increments the internal working queue pointer, and loads the next data required for
transfer from the queue. The internal working queue pointer address is the next com-
mand executed unless the CPU writes a new value first.
If CONT is set and the peripheral chip-select pattern does not change between the cur-
rent and the pending transfer, the PCS pins are continuously driven in their designated
state during and between both serial transfers. If the peripheral chip-select pattern
changes, then the first pattern is driven out during execution of the first transfer, fol-
lowed by the QSPI switching to the next pattern of the second transfer when execution
of the second transfer begins. If CONT is clear, the deselected peripheral chip-select
values (found in register PORTQS) are driven out between transfers.
DT causes a delay to occur after the specified serial transfer is completed. The length
of the delay is determined by DTL. When DT is clear, the standard delay (1 μs at a
16.78-MHz system clock) occurs after the specified serial transfer is completed.
4.4.1.2 Master Wraparound Mode
When the QSPI reaches the end of the queue, it always sets the SPIF flag whether
wraparound mode is enabled or disabled. An optional interrupt to the CPU is generat-
ed when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wrap-
around mode is enabled. A description of SPIFIE may be found in
4.3.3 QSPI Control
Register 2 (SPCR2)
.
In wraparound mode, the QSPI cycles through the queue continuously. Each time the
end of the queue is reached, the SPIF flag is set. If the CPU fails to clear SPIF it re-
mains set, and the QSPI continues to send interrupt requests to the CPU (assuming
SPIFIE is set). The user may avoid causing CPU interrupts by clearing SPIFIE. As
SPIFIE is buffered, clearing it after the SPIF flag is asserted does not immediately stop
the CPU interrupts, but only prevents future interrupts from this source. To clear the
current interrupt, the CPU must read QSPI register SPSR SPSR with SPIF asserted,
followed by a write to SPSR with a zero in SPIF (clear SPIF).
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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