參數(shù)資料
型號(hào)： QSMRM
英文描述： QSMRM QSM Queued Serial Module Reference Manual
中文描述： QSMRM QSM排隊(duì)串行模塊參考手冊(cè)
文件頁(yè)數(shù)： 65/112頁(yè)
文件大小： 1496K
代理商： QSMRM
QSM
REFERENCE MANUAL
SCI SUBMODULE
MOTOROLA
5-9
amble, consisting of ten (or eleven) contiguous ones, is automatically transmitted
whenever TE is changed from zero to one. Refer to
5.3 Transmitter Operation
for a
detailed description of TE and the SCI transmit operation.
RE — Receiver Enable
1 = SCI receiver enabled
0 = SCI receiver disabled
RE enables the SCI receiver when set. When disabled, the receiver status bits RDRF,
IDLE, OR, NF, FE, and PF are inhibited and are not asserted by the SCI. Refer to
5.4
Receiver Operation
for a complete description of RE and the SCI receiver operation.
RWU — Receiver Wakeup
1 = Wakeup mode enabled, all received data ignored until awakened
0 = Normal receiver operation, all received data recognized
Setting RWU enables the wakeup function, which allows the SCI to ignore received
data until awakened by either an idle line or address mark (as determined by WAKE).
When in wakeup mode, the receiver status flags are not set, and interrupts are inhib-
ited. This bit is cleared automatically (returned to normal mode) when the receiver is
awakened.
SBK — Send Break
1 = Break frame(s) transmitted after completion of the current frame
0 = Normal operation
SBK provides the ability to transmit a break code (ten or eleven contiguous zeros) from
the SCI. When SBK is set, the SCI completes the current frame transmission (if it is
transmitting) and then begins transmitting continuous frames of ten (or eleven) zeros
until SBK is cleared. If SBK is toggled by writing it first to a one and then immediately
to a zero (in less than one serial frame interval), the transmitter sends only one or two
break frames before reverting to mark (idle line) or before commencing to send data.
SBK is normally used to broadcast the termination of a transmission.
5.2.3 SCI Status Register (SCSR)
SCSR contains flags that the SCI sets to inform the user of various operational condi-
tions. These flags are automatically cleared either by hardware or by a special ac-
knowledgment sequence consisting of an SCSR read (either the upper byte, the lower
byte, or the entire word) with a flag bit set, followed by a read (or write in the case of
flags TDRE and TC) of data register SCDR (either the lower byte, or the entire word).
An upper byte access of SCDR is only meaningful for reads. Note that a long-word
read can consecutively access both registers SCSR and SCDR. This action clears the
receive status flag bits that were set at the time of the read, but does not clear the
TDRE or TC flags. To clear TDRE or TC, the SCSR read must be followed by a write
to register SCDR (either the lower byte or the entire word).
If an internal SCI signal for setting a status bit comes after the CPU has read the as-
serted status bits but before the CPU has written or read register SCDR, the newly set
status bit is not inadvertently cleared. Instead, register SCSR must be read again with
the status bit set, and register SCDR must be written or read before the status bit is
cleared.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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