
QSM
REFERENCE MANUAL
FUNCTIONAL OVERVIEW
MOTOROLA
1-3
Figure 1-2 QSM Memory Map
The supervisor-only data space segment contains the QSM global registers. These
registers define parameters needed by the QSM to integrate with the MCU. Access to
these registers is permitted only when the CPU is operating in supervisor mode (CPU
status register, S-bit = 1).
Assignable data space can be either restricted to supervisor-only access or unrestrict-
ed to both supervisor and user accesses. The supervisor (SUPV) bit in the QSM mod-
ule configuration register (QSMCR) designates the assignable data space as either
supervisor or unrestricted. If SUPV is set, then the space is designated as supervisor-
only space. Access is then permitted only when the CPU is operating in supervisor
mode. All attempts to read supervisor data spaces when not in supervisor mode (CPU
status register, S-bit = 0) return a value of zero, and all attempts to write have no effect.
If SUPV is clear, both user and supervisor accesses are permitted. To clear SUPV in
the QSMCR, the CPU must be in supervisor mode (CPU status register, S-bit = 1). Re-
fer to Processing States in the appropriate CPU manual for more information on su-
pervisor mode.
The QSM assignable data space segment contains the submodules, QSPI and SCI,
control/status registers, and the QSPI RAM. All registers and RAM may be accessed
$YFFD00-1F
$YFFD20-3F
$YFFD40-4F
$YFFC20-FF
15 7 0
QSMCR
$YFFC00
$YFFC02
QTEST
SUPERVISOR-ONLY DATA SPACE
$YFFC04
QILR
QIVR
$YFFC06
RESERVED
$YFFC08
SCCR0
$YFFC0A
SCCR1
$YFFC0C
SCSR
$YFFC0E
SCDR
$YFFC10
RESERVED
$YFFC12
RESERVED
$YFFC14
RESERVED
PORTQS
$YFFC16
PQSPAR
DDRQS
ASSIGNABLE DATA SPACE
$YFFC18
SPCR0
(SUPERVISOR-ONLY OR UNRESTRICTED)
$YFFC1A
SPCR1
$YFFC1C
SPCR2
$YFFC1E
SPCR3
SPSR
RESERVED
RECEIVE RAM
TRANSMIT RAM
QUEUE RAM
COMMAND RAM
Y = m111 where m is the modmap bit in the SIM MCR (Y = $7 or $F).
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.