參數(shù)資料
型號(hào)： QSMRM
英文描述： QSMRM QSM Queued Serial Module Reference Manual
中文描述： QSMRM QSM排隊(duì)串行模塊參考手冊(cè)
文件頁(yè)數(shù)： 16/112頁(yè)
文件大小： 1496K
代理商： QSMRM
MOTOROLA
2-2
SIGNAL DESCRIPTIONS
QSM
REFERENCE MANUAL
2.2 QSPI Pins
Seven pins are associated with the QSPI. When not needed for a QSPI application,
they may be configured as general-purpose I/O pins.
Table 2-2
identifies the QSPI
pins and their functions. QSM register DDRQS determines whether the pins are des-
ignated as input or output. The user must initialize DDRQS for the QSPI to function
correctly.
2.2.1 PCS[3:0] — Peripheral Chip-Selects
These bidirectional signals provide QSPI peripheral chip-selects.
2.2.2 SS — Slave Select
Assertion of this bidirectional signal selects the QSPI when in slave mode. This is the
same pin as PCS0.
2.2.3 SCK — QSPI Serial Clock
This bidirectional signal furnishes the clock from the QSPI in Master mode or furnishes
the clock to the QSPI in slave mode.
2.2.4 MISO — Master In Slave Out
This bidirectional signal furnishes serial data input to the QSPI in master mode, and
serial data output from the QSPI in slave mode.
2.2.5 MOSI — Master Out Slave In
This bidirectional signal furnishes serial data output from the QSPI in master mode,
and serial data input to the QSPI in slave mode.
Table 2-2 External Pin Inputs/Outputs to the QSPI
Pin Names
Mnemonics
MISO
Mode
Master
Slave
Master
Slave
Master
Slave
Master
Master
Slave
Master
Function
Master In Slave Out
Serial Data Input to QSPI
Serial Data Output from QSPI
Serial Data Output from QSPI
Serial Data Input to QSPI
Clock Output from QSPI Clock
Input to QSPI
Outputs Select Peripheral(s)
Output Selects Peripheral(s)
Input Selects the QSPI
May Cause Mode Fault
Master Out Slave In
MOSI
Serial Clock
SCK
1
NOTES:
1. All QSPI pins (except SCK) can be used as general-purpose I/O if they are not used by the QSPI while the QSPI
is operating.
2. An output (PCS0) when the QSPI is in master mode.
3. An input (SS) when the QSPI is in slave mode.
4. An input (SS) when the QSPI is in master mode; useful in multimaster systems.
Peripheral Chip-Selects
Peripheral Chip-Select
2
Slave Select
3
Slave Select
4
PCS[3:1]
PCS0/
SS
SS
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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