
MOTOROLA
5-6
SCI SUBMODULE
QSM
REFERENCE MANUAL
More accurate baud rates can be obtained by varying the system clock frequency with
the VCO synthesizer. Each VCO speed increment adjusts the baud rate up or down
by 1/64; or 1.56%.
5.2.2 SCI Control Register 1 (SCCR1)
SCCR1 contains parameters for configuration of the SCI. The CPU can read and write
this register at any time. The SCI may modify the RWU bit in some circumstances. In
general, the interrupts enabled by these control bits are cleared by reading the status
register SCSR, followed by reading (for receiver status bits) or by writing (for transmit-
ter status bits) the data register SCDR. For further detail refer to
5.3 Transmitter Op-
eration
and
5.4 Receiver Operation
, respectively.
Bit 15 — Not Implemented
LOOPS — LOOP Mode
1 = Test SCI operation, looping, feedback path enabled
0 = Normal SCI operation, no looping, feedback path disabled
LOOPS controls a feedback path on the data serial shifter. If enabled, the output of the
SCI transmitter is fed back into the receive serial shifter as receiver input, and no data
is driven out of the TXD pin nor is data received from the RXD pin. The TXD pin is driv-
en high (idle line). Both the transmitter and receiver must be enabled for loop mode to
function.
WOMS — Wired-OR Mode for SCI Pins
1 = If configured as an output, TXD is an open-drain output.
0 = If configured as an output, TXD is a normal CMOS output.
WOMS determines whether the TXD pin is an open-drain output or a normal CMOS
output. This bit is used only when TXD is an output. If the TXD pin is being used as a
general-purpose input pin, WOMS has no effect.
ILT — Idle-Line Detect Type
1 = Long idle-line detect (starts counting when the first one is received after a stop
bit(s))
0 = Short idle-line detect (starts counting when the first one is received)
ILT determines which one of two types of idle-line detection is to be used by the SCI
receiver. The short idle-line detection circuitry causes the SCI receiver to start count-
ing ones at any point (even during the frame), which means that the stop bit and any
contiguous one data bits at the end of the last byte are counted toward the 10 or 11
ones in an idle frame. Hence, the data content of the last byte transmitted may affect
the timing of idle-line detection.
The long idle-line detection circuitry causes the SCI receiver to start counting ones
right after a stop bit, which means that the stop bit and any contiguous one data bits
SCCR1
— SCI Control Register 1
$YFFC0A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
LOOPS WOMS
ILT
PT
PE
M
WAKE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.