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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 70/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
5-14
SCI SUBMODULE
QSM
REFERENCE MANUAL
= 0), then normal shifting continues until the word in progress with stop bit(s) is sent.
The preamble (an all ones frame) is then transmitted.
When TE is cleared, the transmitter is disabled only after all pending information is
transmitted, including any data in the transmit serial shifter (inclusive of the stop bit),
any queued preamble (idle frame), or any queued break (logic zero frame). The TC
flag is set, and the TXD pin reverts to control by PORTQS and DDRQS. This function
allows the user to terminate a transmission sequence in the following manner. After
loading the last byte into register TDR and receiving the interrupt from TDRE in SCSR,
(indicating that the data has transferred into the transmit serial shifter), the user clears
TE. The last frame is transmitted normally, and the TXD pin reverts to control by
PORTQS and DDRQS.
To insert a delimiter between two messages and place the nonlistening receivers in
wakeup mode or to signal a retransmission (by forcing an idle line), TE is set to zero
and then to one before the word in the transmit serial shifter has completed transmis-
sion. The transmitter waits until that word is transmitted and then starts transmission
of a preamble (ten or eleven contiguous ones). After the preamble is transmitted, and
if TDRE is set (no new data to transmit), the line continues to mark (remain high). Oth-
erwise, normal transmission of the next word begins.
Two SCI messages may be separated with minimum idle time by using a preamble of
ten bit-times (eleven if a 9-bit data format is specified) of marks (logic ones). The entire
process can occur using the following procedure:
A. Write the last byte of the first message to the TDR.
B. Wait for TDRE to go high, indicating that the last byte is transferred to the trans-
mit serial shifter.
C. Clear TE and then set TE back to one. This queues the preamble to follow the
stop bit of the current transmission immediately.
D. Write the first byte of the second message to register TDR.
In this sequence, if the first byte of the second message is not transferred to register
TDR prior to the finish of the preamble transmission, then the transmit data line (TXD
pin) simply marks idle (logic one) until TDR is finally written. Also, if the last byte of the
first message finishes shifting out (including the stop bit) and TE is clear, TC will go
high and transmission will be considered complete. The TXD pin reverts to being a
general-purpose I/O line.
The CPU writes data to be transmitted to register TDR, which automatically loads the
data into the transmit serial shifter. Before writing to TDR, the user should check TDRE
in SCSR. If TDRE = 0, then data is still waiting to be sent to the transmit serial shifter.
Writing to TDR with TDRE clear overwrites previous data to be transferred. If TDRE =
1, then register TDR is empty, and new data may be written to TDR clearing TDRE.
As soon as the data in the transmit serial shifter has shifted out and if a new byte of
data is in TDR (TDRE = 0), then the new data is transferred from register TDR to the
transmit serial shifter, and TDRE is automatically set. An interrupt may optionally be
generated at this point.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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