- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361324 > QSMRM QSMRM QSM Queued Serial Module Reference Manual PDF資料下載
參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 77/112頁 |
| 文件大小： | 1496K |
| 代理商： | QSMRM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁當(dāng)前第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
QSM
REFERENCE MANUAL
SCI SUBMODULE
MOTOROLA
5-21
All status flags associated with a serially received frame are set simultaneously and at
a time that does not interfere with CPU access to the affected registers. When a com-
pleted frame is received, either the RDRF or OR flag is always set. If RIE in SCCR1 is
set, an interrupt results whenever RDRF is set. The receiver status flags NF, FE, and
PF are set simultaneously with RDRF, as appropriate. These receiver flags are never
set with OR because the flags only apply to the data in the receive serial shifter. The
receiver status flags do not have separate interrupt enables, since they are set simul-
taneously with RDRF and must be read by the user at the same time as RDRF.
All receiver status flags are cleared by the following sequence. Register SCSR is read
first, followed by a read of register SCDR. Reading SCSR not only informs the CPU of
the status of the received data, but also arms the clearing mechanism. Reading SCDR
supplies the received data to the CPU and clears all of the status flags: RDRF, IDLE,
OR, NF, FE, and PF.
5.4.2.1 Idle-Line Detect
The receiver hardware includes the ability to detect an idle line. This function can be
used to indicate when a group of serial transmissions is finished. An idle line is defined
as a minimum of ten bit-times (or eleven if a 9-bit data format is selected) of contiguous
ones on the RXD pin. During a typical serial transmission, frames are transmitted iso-
chronously, that is, no idle time occurs between frames. Even if all data bits in a frame
are logic ones, the start bit ensures that at least one logic zero bit-time occurs for each
frame.
Motorola MCUs from the M68HC11 and M68HC05 Families have SCIs with only one
type of idle-line detect circuitry. On these MCUs, the receiver bit processor starts
counting logic one bit-times at any point (even within a frame). This method allows the
earliest recognition of an idle line because the stop bit and any contiguous ones pre-
ceding the stop bit are counted with the logic ones in the idle line following the stop bit.
In some applications, the CPU overhead prevents the servicing of interrupts as soon
as possible to ensure that no bit-time of an idle line occurs between frames. Although
this idle line causes no deterioration of the message content, if one bit-time should oc-
cur after a data byte of all ones, the combination is seen as an idle line and causes
sleeping SCIs to wake up.
The SCI on the QSM module contains this same idle-line detect logic called short idle-
line detect as well as long idle-line detect. In long idle-line detect mode, the SCI begins
counting logic ones after the stop bit is received. The data content of a byte, therefore,
does not affect how quickly the idle line is detected. When RXD goes idle for the min-
imum required time, the IDLE flag in SCSR is set. ILT in SCCR1 is used to choose be-
tween short and long idle-line detection.
If ILIE in SCCR1 is set, a hardware interrupt request is generated when the IDLE flag
is set. This flag is cleared by reading SCSR with IDLE set, followed by reading register
RDR. The IDLE flag is not set again until after at least one frame has been received
(RDRF = 1), which prevents an extended idle interval from causing more than one in-
terrupt.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QSOP-24 | Package MQA24 |
| QST4 | Low frequency amplifier |
| QST9 | General purpose amplification (−30V, −1A) |
| QSX7 | General purpose amplification (12V, 1.5A) |
| QSZ1 | General purpose transistor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QSMS-0136 | 制造商:Avago Technologies 功能描述:SCHOTTKY DIODE, PART NUMBER ASSIGNED TO REPLACE HSMS-0005 - Gel-pak, waffle pack, wafer, diced wafer on film |
| QSMS-2926-TR1G | 制造商:Avago Technologies 功能描述:SCHOTTKY DIODE - Tape and Reel |
| QSMT-AW13-NSUZ1 | 制造商:Avago Technologies 功能描述:MS AV,1W CWHITE - Tape and Reel |
| QSMT-FW85-NX000 | 制造商:Avago Technologies 功能描述:THIS HIGH BRIGHTNESS LED LIGHT SOURCE |
| QSMT-L060-227NG | 制造商:Avago Technologies 功能描述:L2 LED CONTOUR LIGHTING,COLORLESS - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。