- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361324 > QSMRM QSMRM QSM Queued Serial Module Reference Manual PDF資料下載
參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 39/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
QSM
REFERENCE MANUAL
QSPI SUBMODULE
MOTOROLA
4-11
tion of either flag causes the QSPI to send a hardware interrupt to the CPU. When
HMIE is clear, the asserted flag does not cause an interrupt.
HALT — Halt
1 = Halt enabled
0 = Halt not enabled
This bit is used by the CPU to stop the QSPI on a queue boundary. The QSPI halts in
a known state from which it can later be restarted. When HALT is asserted by the CPU,
the QSPI finishes executing the current serial transfer (up to 16 bits) and then halts.
While halted, if the command control bit (CONT of the QSPI RAM) for the last com-
mand was asserted, the QSPI continues driving the peripheral chip-select pins with the
value designated by the last command before the halt. If CONT was clear, the QSPI
drives the peripheral chip-select pins to the value in QSM register PORTQS.
If HALT is asserted during the last command in the queue, the QSPI completes the
last command, asserts both HALTA and SPIF, and clears SPE. If the last queue com-
mand has not been executed, asserting HALT does not set SPIF nor clear SPE. QSPI
execution continues when the CPU clears HALT.
4.3.5 QSPI Status Register (SPSR)
SPSR contains QSPI status information. Only the QSPI can assert the bits in this reg-
ister. The CPU reads this register to obtain status information and writes this register
to clear status flags. CPU writes to CPTQP have no effect.
* SPCR3 — QSPI Control Register 3
SPIF — QSPI Finished Flag
1 = QSPI finished
0 = QSPI not finished
SPIF is set when the QSPI finishes executing the last command determined by the ad-
dress contained in ENDQP in SPCR2. When the address of the command being exe-
cuted matches the ENDQP, the SPIF flag is set after finishing the serial transfer.
If wraparound mode is enabled (WREN = 1), the SPIF is set, after completion of the
command defined by ENDQP, each time the QSPI cycles through the queue. If SPIFIE
in SPCR2 is set, an interrupt is generated when SPIF is asserted. Once SPIF is set,
the CPU may clear it by reading SPSR followed by writing SPSR with a zero in SPIF.
MODF — Mode Fault Flag
1 = Another SPI node requested to become the network SPI master while the QSPI
was enabled in master mode (MSTR = 1), or the PCS0/SS pin was incorrectly
pulled low by external hardware.
0 = Normal operation
SPSR
— QSPI Status Register
$YFFC1F
15
8
7
6
5
4
3
2
1
0
SPCR3*
SPIF
MODF HALTA
0
CPTQP
RESET:
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QSOP-24 | Package MQA24 |
| QST4 | Low frequency amplifier |
| QST9 | General purpose amplification (−30V, −1A) |
| QSX7 | General purpose amplification (12V, 1.5A) |
| QSZ1 | General purpose transistor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QSMS-0136 | 制造商:Avago Technologies 功能描述:SCHOTTKY DIODE, PART NUMBER ASSIGNED TO REPLACE HSMS-0005 - Gel-pak, waffle pack, wafer, diced wafer on film |
| QSMS-2926-TR1G | 制造商:Avago Technologies 功能描述:SCHOTTKY DIODE - Tape and Reel |
| QSMT-AW13-NSUZ1 | 制造商:Avago Technologies 功能描述:MS AV,1W CWHITE - Tape and Reel |
| QSMT-FW85-NX000 | 制造商:Avago Technologies 功能描述:THIS HIGH BRIGHTNESS LED LIGHT SOURCE |
| QSMT-L060-227NG | 制造商:Avago Technologies 功能描述:L2 LED CONTOUR LIGHTING,COLORLESS - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。