- 您現(xiàn)在的位置：買賣IC網 > PDF目錄361324 > QSMRM QSMRM QSM Queued Serial Module Reference Manual PDF資料下載
參數資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數： | 83/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁當前第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
QSM
REFERENCE MANUAL
USING THE QSPI FOR ANALOG DATA AQUISITION
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
A-5
If DT is set, a user-specified delay elapses before the next serial transfer is begun.
Otherwise, the QSPI executes the next transfer as soon as possible (approximately 1
ms when the MC68332 operates at 16.778 MHz). This delay is useful if a peripheral
needs time to perform a function that affects subsequent serial transfers. One example
might be to wait for an A/D converter to perform a conversion.
The remaining element in the control byte is the bits per transfer enable (BITSE) bit. If
BITSE is set, the transfer length is a user-specified value, ranging from eight to 16 bits.
If BITSE is cleared, the transfer length will default to eight bits.
Figure A-6
represents a programmer's model of the QSPI. The QSM data direction
register (QDDR) determines whether a given QSPI pin is an input or an output. When
read, the QSM port data register (QPDR) provides the logic level present on a QSM
input pin or the data latched in an output pin. When written, the write data is latched
into the output register. The QSM pin assignment register (QPAR) controls whether a
pin is to be controlled by the QSPI or is to function as a general-purpose I/O pin.
Serial peripheral control register 0 (SPCR0) specifies six different functions. The mas-
ter/slave mode select (MSTR) bit, if set, causes the QSPI to operate as the controller
of the SPI transfer. The wired-OR mode for QSPI pins (WOMQ) bit, if set, causes all
QSPI outputs to function in an open-drain mode, requiring external pull-up resistors.
The bits per transfer (BITS) field allows the programmer to specify the number of bits
in a non-default transfer (used if BITSE is set). The clock polarity (CPOL) bit deter-
mines the polarity of the SCK output, and the clock phase (CPHA) bit dictates the da-
ta's phase relationship to the SCK. The serial clock baud rate (BAUD) field determines
the QSPI SCK frequency, from 33 kHz to 4.2 MHz (with the MC68332 system clock
frequency at 16.778 MHz).
Serial peripheral control register 1 (SPCR1) specifies three different functions. Setting
the QSPI enable (SPE) bit causes the QSPI to begin operation; clearing SPE causes
operation to stop immediately. SPE is automatically cleared by the QSPI when it com-
pletes all specified transfers. The DSCKL field allows the programmer to set the non-
default delay before SCK (used if DSCK is set). The DTL field controls the non-default
delay after the transfer is completed (used if DT is set).
Serial peripheral control register 2 (SPCR2) specifies five queue control functions. The
new queue pointer value (NEWQP) field determines which queue entry is to be trans-
ferred first. More queue entries are sequentially transferred until the entry specified by
the ending queue pointer (ENDQP) field is completed. If the wrap enable (WREN) bit
is set, transfers continue either at queue entry 0 or at the entry specified by the
NEWQP field. The point the queue wraps to (entry 0 or NEWQP) is determined by the
wrap to (WRTO) bit. The SPI finished interrupt enable (SPIFIE) bit is an interrupt en-
able. If set, an interrupt will be generated upon completion of the queue entry specified
by the ENDQP field.
F
Freescale Semiconductor, Inc.
n
.
相關PDF資料 |
PDF描述 |
|---|---|
| QSOP-24 | Package MQA24 |
| QST4 | Low frequency amplifier |
| QST9 | General purpose amplification (−30V, −1A) |
| QSX7 | General purpose amplification (12V, 1.5A) |
| QSZ1 | General purpose transistor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| QSMS-0136 | 制造商:Avago Technologies 功能描述:SCHOTTKY DIODE, PART NUMBER ASSIGNED TO REPLACE HSMS-0005 - Gel-pak, waffle pack, wafer, diced wafer on film |
| QSMS-2926-TR1G | 制造商:Avago Technologies 功能描述:SCHOTTKY DIODE - Tape and Reel |
| QSMT-AW13-NSUZ1 | 制造商:Avago Technologies 功能描述:MS AV,1W CWHITE - Tape and Reel |
| QSMT-FW85-NX000 | 制造商:Avago Technologies 功能描述:THIS HIGH BRIGHTNESS LED LIGHT SOURCE |
| QSMT-L060-227NG | 制造商:Avago Technologies 功能描述:L2 LED CONTOUR LIGHTING,COLORLESS - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。