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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 67/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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QSM
REFERENCE MANUAL
SCI SUBMODULE
MOTOROLA
5-11
RAF — Receiver Active Flag
1 = SCI receiver is busy
0 = SCI receiver is idle
RAF indicates whether the SCI receiver is busy. This flag is set when the SCI receiver
detects a possible start bit and is cleared when the chosen type of idle line is detected.
RAF can be used to reduce collisions in systems with multiple masters.
The SCI receiver samples each start bit 16 times (at a rate of 16 times the baud rate).
The 16 sample times are called RT1–RT16. RAF is set initially at RT1. The SCI receiv-
er samples RT3, RT5, and RT7. If the receiver line is high during two or three of the
three receive time (RT) samples, the start bit is considered invalid, and RAF is subse-
quently cleared. A more detailed description is found in
5.4.1 Receiver Bit Processor
.
IDLE — Idle-Line Detected Flag
1 = SCI receiver detected an idle-line condition
0 = SCI receiver did not detect an idle-line condition
IDLE is set when the SCI receiver detects an idle-line condition (reception of a mini-
mum of ten or eleven consecutive ones as specified by ILT in SCCR1). This bit is not
set by the idle-line condition when RWU in SCCR1 is set. Once cleared, IDLE is not
set again until after RDRF is set (after the line is active and becomes idle again). If a
break is received, RDRF is set, allowing a subsequent idle line to be detected again.
IDLE is cleared when SCSR is read with IDLE set, followed by a read of register RDR.
Under certain conditions, the IDLE flag may be set immediately following the negation
of RE (SCCR1). System designs should ensure this causes no detrimental effects.
OR — Overrun Error Flag
1 = RDRF is not cleared before new data arrives
0 = RDRF is cleared before new data arrives
OR is set when a new byte is ready to be transferred from the receive serial shifter to
register RDR, and RDR is already full (RDRF is still set). Data transfer is inhibited until
OR is cleared. Previous data in RDR remains valid, but additional data received during
an overrun condition (including the byte that set OR) is lost.
A difference exists between OR and the other receiver status flags, NF, FE, and PF
all reflect the status of data already transferred to register RDR. OR reflects an oper-
ational condition that resulted in a loss of data to RDR. OR is cleared when SCSR is
read with OR set, followed by a read of register RDR.
NF — Noise Error Flag
1 = Noise occurred on the received data
0 = No noise detected on the received data
NF is set when the SCI receiver detects noise on a valid start bit, on any of the data
bits, or on the stop bit(s). It is not set by noise on the idle line or on invalid start bits.
Each bit is sampled three times for noise. If the three samples are not at the same logic
level, the majority value is used for the received data value, and NF is set. NF is not
set until the entire frame is received and RDRF is set. Although an interrupt is not ex-
plicitly associated with NF, an interrupt may be generated with RDRF and NF checked
in this manner. NF is cleared when SCSR is read with NF set, followed by a read of
register RDR.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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