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參數(shù)資料
| 型號(hào)： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊(cè) |
| 文件頁數(shù)： | 54/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
4-26
QSPI SUBMODULE
QSM
REFERENCE MANUAL
Execution continues in wraparound mode, even while the QSPI is requesting interrupt
service from the CPU. The internal working queue pointer increments to the next ad-
dress, and the commands are executed again. SPE is not cleared by the QSPI. New
receive data overwrites previously received data in the receive data segment.
Wraparound mode is properly exited in two ways: a) The CPU may disable wrap-
around mode by clearing WREN. The next time the end of the queue is reached, the
QSPI sets SPIF, clears SPE, and stops; b) The CPU sets HALT. This second method
halts the QSPI after the current transfer is completed, allowing the CPU to negate
SPE. The CPU can immediately stop the QSPI by clearing SPE; however, this method
is not recommended as it causes the QSPI to abort a serial transfer in process.
4.4.2 Slave Mode
When operating in slave mode, the QSPI may respond to externally initiated serial
transfers. The QSPI is unable to initiate any serial transfers. Slave mode is typically
used when multiple MCUs are in an SPI bus network, because only one device can be
the SPI master (in master mode) at any given time.
QSM register DDRQS should be written to direct data flow on the QSPI pins used. The
MISO and MOSI pins, if needed, should be configured as output and input, respective-
ly. Pins SCK and PCS0/SS should be configured as inputs.
QSM register PQSPAR should be written to assign the necessary bits to the QSPI.
The pins necessary for slave mode operation are MISO and/or MOSI, SCK, and
PCS0/SS. MISO is the data output pin in slave mode, and MOSI is the data input pin
in slave mode. Either or both may be necessary depending on the particular applica-
tion.
The serial clock (SCK) is the slave clock input in slave mode. PCS0/SS is the slave
select pin used to select the QSPI for a serial transfer by the external SPI bus master
when the QSPI is in slave mode. The external bus master selects the QSPI by driving
PCS0/SS low.
When the MISO pin is configured for QSPI use (MISO bit in PQSPAR = 1) and the
QSPI is set up for slave mode (MSTR bit in SPCR0 = 0) the MISO pin can be in a high-
impedance state (three-stated). This occurs while the SS pin is at a logic level one.
This overrides the MISO bit in the DDRQS if it is set to be an output. The MISO pin
becomes active when SS is pulled low.
The command control segment is not implemented in slave mode; therefore, the CPU
does not need to initialize it. This segment of the QSPI RAM and any other unused
segments may be employed by the CPU as general-purpose RAM. Other consider-
ations for initialization are prescribed in
3.1 Overall QSM Configuration Summary.
4.4.2.1 Description of Slave Operation
After reset, the QSM registers and the QSPI control registers must be initialized as de-
scribed above. Although the command control segment is not used, the transmit and
receive data segments may, depending upon the application, need to be initialized. If
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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