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| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 30/112頁 |
| 文件大小： | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
4-2
QSPI SUBMODULE
QSM
REFERENCE MANUAL
4.1.2 Programmable Peripheral Chip-Selects
Four peripheral chip-select pins allow the QSPI to access up to 16 independent pe-
ripherals by decoding the four peripheral chip-select signals. Up to four independent
peripherals can be selected by direct connection to a chip-select pin. The peripheral
chip-selects simplify interfacing to two or more serial peripherals by providing dedicat-
ed peripheral chip-select signals, alleviating the need for CPU intervention.
4.1.3 Wraparound Transfer Mode
Wraparound transfer mode allows automatic, continuous re-execution of the prepro-
grammed queue entries. Newly transferred data replaces previously transferred data.
Wraparound simplifies interfacing with A/D converters by automatically providing the
CPU with the latest A/D conversions in the QSPI RAM. Consequently, serial peripher-
als appear as memory-mapped parallel devices to the CPU.
4.1.4 Programmable Transfer Length
The number of bits in a serial transfer is programmable from eight to 16 bits, inclusive.
For example, ten bits could be used for communicating with an external 10-bit A/D
converter. Likewise, a vacuum fluorescent display driver might require a 12-bit serial
transfer. The programmable length simplifies interfacing to serial peripherals that re-
quire different data lengths.
4.1.5 Programmable Transfer Delay
An inter-transfer delay may be programmed from approximately 1 to 500 μs (using a
16.78-MHz system clock). For example, an A/D converter may require time between
transfers to complete a new conversion. The default delay is 1 μs (17 clocks at 16.78-
MHz). The programmable length of delay simplifies interfacing to serial peripherals
that require delay time between data transfers.
4.1.6 Programmable Queue Pointer
The QSPI has a pointer that identifies the queue location containing the data for the
next serial transfer. The CPU can switch from one task to another in the QSPI by writ-
ing to the queue pointer, changing the location in the queue that is to be transferred
next. Otherwise, the pointer increments after each serial transfer. By segmenting the
queue, multiple-task support can be provided by the QSPI.
4.1.7 Continuous Transfer Mode
The continuous transfer mode allows the user to send and receive an uninterrupted bit
stream with a peripheral. A minimum of 8 bits and a maximum of 256 bits may be trans-
ferred in a single burst without CPU intervention. Longer transfers are possible; how-
ever, minimal CPU intervention is required to prevent loss of data. A 1 μs pause (using
a 16.78-MHz system clock) is inserted between each queue entry transfer.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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