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參數資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數： | 38/112頁 |
| 文件大小： | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
4-10
QSPI SUBMODULE
QSM
REFERENCE MANUAL
Bits [7:4] — Not Implemented
NEWQP — New Queue Pointer Value
NEWQP determines which queue entry the QSPI transfers first. NEWQP should be ini-
tialized before the QSPI is enabled with SPE. NEWQP may also be written while the
QSPI is operating. When this happens, the QSPI completes transfer of the queue entry
in progress and then immediately begins transferring queue entries starting with the
entry indicated by the NEWQP.
In this way, NEWQP provides additional functionality to the QSPI by providing a mech-
anism for supporting multiple queues or subqueues within the QSPI RAM. By chang-
ing the value in NEWQP, the user can cause the QSPI to execute a sequence of QSPI
commands beginning at any location in the queue. Therefore, the user is able to set
up in advance separate subqueues for different tasks within the QSPI RAM. By writing
to NEWQP, selection between the different subqueues within the QSPI RAM is ac-
complished.
If wraparound mode is enabled by setting WREN and WRTO in SPCR2, NEWQP as-
sumes an additional function. When the end of the queue is reached, as determined
by ENDQP, the address contained in NEWQP is used by the QSPI to wrap around to
the first queue entry. The QSPI then re-executes the queued commands repeatedly
until halted.
4.3.4 QSPI Control Register 3 (SPCR3)
SPCR3 contains parameters for configuring the QSPI. The CPU can read and write
this register; the QSM has read-only access.
* SPSR — QSPI Status Register
Bits [15:11] — Not Implemented
LOOPQ — QSPI Loop Mode
1 = Feedback path enabled
0 = Feedback path disabled
LOOPQ enables or disables the feedback path on the data serializer for testing. If en-
abled, LOOPQ routes serial output data back into the data serializer, instead of re-
ceived data. If disabled, LOOPQ allows regular received data into the data serializer.
LOOPQ does not affect the QSPI output pins.
HMIE — HALTA and MODF Interrupt Enable
1 = HALTA and MODF interrupts enabled
0 = HALTA and MODF interrupts disabled
HMIE enables or disables QSPI interrupts to the CPU caused when either the HALTA
status flag or the MODF status flag in SPSR is asserted. When HMIE is set, the asser-
SPCR3
— QSPI Control Register
$YFFC1E
15
14
13
12
11
10
9
8
7
0
0
0
0
0
0
LOOPQ
HMIE
HALT
SPSR*
RESET:
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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