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參數資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數： | 36/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
4-8
QSPI SUBMODULE
QSM
REFERENCE MANUAL
Delay after transfer = [(32 *
DTL)/system clock frequency]
(4-4)
where DTL equals {1, 2, 3,... 255}.
NOTE
A zero value for DTL causes a delay-after-transfer value of (32 *
256)/system clock, which equals 488.5 μs with a 16.78-MHz system
clock.
If DT equals zero, a standard delay is inserted.
Standard Delay-after-Transfer = [17/System Clock]
(4-5)
= 1 μs with a 16.78-MHz System Clock
Delay after transfer can be used to ensure that the deselect time requirement (for pe-
ripherals having such a requirement) is met. Some peripherals must be deselected for
a minimum period of time between consecutive serial transfers. A delay after transfer
can be inserted between consecutive transfers to a given peripheral to ensure that its
minimum deselect time requirement is met or to allow serial A/D converters to com-
plete conversion before the next transfer is made.
4.3.3 QSPI Control Register 2 (SPCR2)
SPCR2 contains parameters for configuring the QSPI. Although the CPU can read and
write this register, the QSM has read access only. Writes to this register are buffered.
A write to SPCR2 that changes any of the bit values (while the QSPI is operating) is
ineffective on the current serial transfer, but becomes effective on the next serial trans-
fer. Reads of SPCR2 return the actual current value of the register, not the buffer. Re-
fer to
4.4 Operating Modes and Flowcharts
for a detailed description of this register.
SPIFIE — SPI Finished Interrupt Enable
1 = QSPI interrupts enabled
0 = QSPI interrupts disabled
SPIFIE enables the QSPI to generate a CPU interrupt upon assertion of the status flag
SPIF. Because it is buffered, the value written to SPIFIE applies only upon completion
of the queue (the transfer of the entry indicated by ENDQP). Thus, if a single sequence
of queue entries is to be transferred (i.e., no WRAP), then SPIFIE should be set to the
desired state before the first transfer.
If a subqueue (see bit NEWQP) is to be used, the same CPU write that causes a
branch to the subqueue may enable or disable the SPIF interrupt for the subqueue.
The primary queue retains its own selected interrupt mode, either enabled or disabled.
SPCR2
— QSPI Control Register 2
$YFFC1C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPIFIE
WREN WRTO
0
ENDQP
0
0
0
0
NEWQP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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