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參數(shù)資料
| 型號(hào)： | MC68328PV |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 76/198頁(yè) |
| 文件大?。?/td> | 551K |
| 代理商： | MC68328PV |
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Phase-Locked Loop and Power Control
15-8
MC68328 USER’S MANUAL 11/10/97
MOTOROLA
PHASE-LOCKED
LOOP
3
AND
POWER
CONTROL
PRELIMINARY
STOP
This bit immediately enters the power-save mode without waiting for the power controller to
cycle through a complete burst period. This bit disables the CPU clock after the bus cycle
that follows the next CLK32 rising edge. When the system is to enter the doze mode, this bit
is set. On the next burst period, or interrupt, the clock will restart for its allotted period. This
bit is reset to zero and is cleared on wake-up events.
1 = Stop CPU clock (enter doze mode)
0 = Normal CPU clock bursts
WIDTH
Width of CPU clock bursts. These bits reset to 11111 ($1F).
00000 = 0/31 duty cycle
00001 = 1/31 duty cycle
00010 = 2/31 duty cycle
...
11111 = 31/31 duty cycle
These bits control the width of the CPU clock bursts in 1/31 increments. While the WIDTH
is 1 and the power controller is enabled, the clock is bursted to the CPU at a duty cycle of
1/31. While the WIDTH bits are 1F(hex), the clock is always on. While the WIDTH is zero,
the clock is always off. Set the WIDTH to 0 when the CPU should be disabled for extended
time periods, but it can be awakened without waiting for the PLL to re-acquire lock.
These bits are not affected by clearing the PC EN bit. When an interrupt disables the power
controller, these bits are not changed. Users should enter the doze mode by setting the
PCEN or STOP bit after an interrupt has been serviced. Typically, it is the STOP bit that is
set.
15.3.3 Operation
This section describes how to use the variable duty-cycle or STOP bit in the power controller
to enter doze mode.
15.3.3.1 NORMAL OPERATION
When the MC68328 processor begins operation after reset, the power controller is disabled
and the MC68EC000 internal clock runs continuously. To reduce the power consumed by
the MC68EC000, the power controller is enabled when the STOP or PCEN bit is set. The
value in the WIDTH register determines the duty cycle of the clock-bursts that are applied
to the MC68EC000 when PCEN is set. If an interrupt is received, the power controller is
automatically disabled. It is up to the interrupt-service routine to re-enable the power
controller.
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