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參數(shù)資料
| 型號(hào)： | MC68328PV |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 177/198頁(yè) |
| 文件大?。?/td> | 551K |
| 代理商： | MC68328PV |
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Signals
2-5
MC68328 USER’S MANUAL 11/6/97
MOTOROLA
SIGNAL
DESCRIPTIONS
2
PRELIMINARY
PB7–PB0/D7–D0
This bus is the lower data byte or general-purpose I/O. In pure 8-bit systems, this bus can
serve as a general-purpose I/O. The WDTH8 bit in the system control register ($FFF000)
should be set to one (1) by software before the port can be used. In 16-bit or mixed 8-/16-
bit systems, these pins must function as the lower data byte.
2.1.6 Bus Control Pins
AS—ADDRESS STROBE
This active-low output signal indicates that a valid address is present on the address bus. It
is not asserted during LCD DMA accesses.
R/W—READ/WRITE
This output signal defines the data bus transfer as a read or write cycle; read = 1; write = 0.
PC1/UDS—UPPER DATA STROBE/PORT C I/O
This pin can be programmed as UDS or as a general-purpose I/O. When used as upper data
strobe (UDS) output, this active-low signal is asserted when the internal EC000 core does
a 16-bit word access or an even byte access. It is not asserted during LCD DMA accesses.
PC2/LDS—LOWER DATA STROBE/PORT C I/O
This pin can be programmed as LDSor as a general-purpose I/O. When used as lower data
strobe (LDS) output, this active-low signal is asserted when the internal EC000 core does a
16-bit word access or an odd byte access. It is not asserted during LCD DMA accesses.
LWE, UWE — LOWER BYTE WRITE-ENABLE AND UPPER BYTE WRITE-ENABLE
On a write cycle to a 16-bit port, these active-low output signals indicate when the upper or
lower 8 bits of the data bus contain valid data. In 8-bit mode or when the BSW bit in the chip-
select register is 0, use only the upper write-enable (UWE) for write-enable control.
PC4/IRQ7—LEVEL 7 INTERRUPT/PORT C I/O
When programmed as peripherals, this signal is an active-low input which, when asserted,
will generate a level 7 interrupt to the CPU. When programmed as I/O, it becomes the PC 4
parallel I/O port.
PC5/DTACK—DATA TRANSFER ACKNOWLEDGE, PC5
This pin can be programmed as parallel I/O PC5 or DTACK. While programmed as DTACK,
this input signal indicates that the data transfer has been completed. DTACK is normally
generated internally for all chip-selects. For systems that address spaces outside of the
chip-select ranges, DTACK must be generated externally. PC5/DTACK must have an
external pull-up resistor if programmed for the DTACK function.
OE—OUTPUT-ENABLE
This active-low signal is asserted during a read cycle of the MC68328 processor, which
enables the output of either ROM or SRAM. This signal also serves the PCMCIA 1.0
interface to indicate a read cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
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