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參數(shù)資料
| 型號(hào)： | MC68328PV |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 60/198頁(yè) |
| 文件大?。?/td> | 551K |
| 代理商： | MC68328PV |
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Serial Peripheral Interface—Slave
13-2
MC68328 USER’S MANUAL 11/10/97
MOTOROLA
SERIAL
PERIPHERAL
9
INTERFACE–SLAVE
PRELIMINARY
13.1 OPERATION
Users first initialize the SPI slave (SPIS) program register. The SPIS then waits for the input-
enable (SPSEN) and clock (SPSCLK) to control the data transfer. The shift register fills with
data over the next 8 clock cycles. On the eighth clock, the shift register contents loads into
the data buffer. The SPISIRQ bit is set, posting an interrupt. The valid data in the buffer
awaits the service routine access.
The clock input performs shifts depending on phase and polarity. In phase 0 mode(PHA=0),
serial data are strobed on the leading edges of SPSCLK. In phase 1 mode(PHA=1), data
are strobed in on trailing edges. The polarity (POL) specifies the inactive state value of
SPSCLK. While POL=1, the idle state of the SPSCLK is high. While POL = 0, the idle state
of the SPSCLK is low. This flexibility allows operation with most serial peripheral devices on
the market.
If enabled, the SPIS operates even if the system clock is inactive. After the SPIS receives a
data byte from an external master, the SPIS interrupt is posted. If the system is in sleep
mode, this interrupt can initiate the wakeup sequence for restoring the system clock. The
SPIS bit (bit 21) in the wakeup control register IWR (at location 0x(FF)FFF308) must be set
for the wakeup sequence to occur.
13.2 SIGNAL DESCRIPTIONS
SPSRXD
This pin is the serial data input to the shift register. A new bit is shifted in on each leading
edge of SPSCLK while in normal mode(POL=0) or on each trailing edge of SPSCLK in
polarity-inverted mode(POL=1). This signal pin is multiplexed with other signals to port K, bit
4. Refer to Section 7.1.10 for more details.
SPSCLK
This pin is the shift clock input.
SPSEN
This pin indicates that an SPI transfer is in progress. After the enable becomes active, the
SPIS state machine responds to clock edges for data transfer.
13.3 SPI SLAVE REGISTER
This register controls the SPIS operation and reports its status. The data register contains
the data transmitted by the external master. After reset, all bits are set to $0000.
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