
Interrupt Controller
MOTOROLA
MC68328 USER’S MANUAL 12/9/97
6-5
INTERRUPT
6
CONTROLLER
PRELIMINARY
handler. The interrupt service routine should end with the rte instruction, which restores the
processing state prior to the interrupt.
The DragonBall provides one interrupt vector for each of the seven user interrupt levels.
These interrupt vectors form the user interrupt vector section of Table 6-1. The user interrupt
vectors can be located anywhere within the address range 0x100 to 0x400. You can
program the five most-significant bits of the interrupt vector number, but the lower three bits
reflect the interrupt level that is being serviced. All interrupts are maskable by the interrupt
controller. If an interrupt is masked, its status can still be accessed in the interrupt pending
register (IPR).
6.4 VECTOR GENERATOR
The interrupt controller provides a vector number to the core. You can program the upper
five bits of the interrupt vector register (IVR) to allow the interrupt vector number to point to
any address in the exception vector table. However, many of the vector addresses are
assigned to the core’s internal exceptions and cannot be reused. This leaves only a small
range of address space (from 0x100 through 0x400) where you can configure the IVR to
locate user interrupt vectors. For example, if you write a value of 0x40 to the IVR, the
interrupt vector base is set to point to 0x100 (0x40<<2), which is the beginning of the user
interrupt vectors shown in Table 6-1. The coding for the vector numbers is provided in
Table 6-2.
6.5 PROGRAMMING MODEL
This section describes registers that you may need to configure so that the interrupt
controller can properly process interrupts, generate vector numbers, and post interrupts to
the core.
Table 6-2. Interrupt Vector Numbers
INTERRUPT
VECTOR NUMBER
Level 7
xxxxx111
Level 6
xxxxx110
Level 5
xxxxx101
Level 4
xxxxx100
Level 3
xxxxx011
Level 2
xxxxx010
Level 1
xxxxx001
NOTE: xxxxx is replaced by the upper five bits of the
interrupt vector register.