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參數(shù)資料
| 型號(hào)： | MC68328PV |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 150/198頁(yè) |
| 文件大?。?/td> | 551K |
| 代理商： | MC68328PV |
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Interrupt Controller
6-14
MC68328 USER’S MANUAL 12/9/97
MOTOROLA
MODULE
INTERRUPT
6
CONTROLLER
PRELIMINARY
IRQ6—Wake-up IRQ6 Interrupt
0 = Disallow IRQ6 interrupt from waking up the processor.
1 = Enable IRQ6 interrupt to wake up the processor (default at reset).
PEN—Wake-up Pen Interrupt
0 = Disallow pen-down interrupt from waking up the processor.
1 = Enable pen-down interrupt to wake up the processor (default at reset).
SPIS—Wake-up Serial Peripheral Interface (SPI) Slave Interrupt
0 = Disallow SPI slave interrupt from waking up the processor.
1 = Enable SPI slave interrupt to wake up the processor (default at reset).
TMR1—Wake-up Timer 1 Interrupt
0 = Disallow timer 1 interrupt from waking up the processor.
1 = Enable timer 1 interrupt to wake up the processor (default at reset).
IRQ7—Wake-up IRQ7 Interrupt
0 = Disallow IRQ7 interrupt from waking up the processor.
1 = Enable IRQ7 interrupt to wake up the processor (default at reset).
6.5.5 Interrupt Status Register
During the interrupt service, the interrupt handler can determine the source of the interrupt
by examining the interrupt status register (ISR). Each bit in this register, when set, indicates
the corresponding interrupt is posted to the core. If there are multiple interrupt sources at
the same level, the software handler may need to prioritize them, depending on the
application.
Each interrupt status bit in the interrupt status register reflects the interrupt request from their
respective interrupt sources. Refer to the specific sections about the timer, SPI master, SPI
slave, real-time clock, and pulse-width modulation for details about how to clear the
interrupt. The IRQ7 signal is an active-low edge-triggered interrupt request and an IRQ7
interrupt is clear by writing a 1 to the IRQ7 status bit. When programmed as edge-triggered
interrupts, IRQ1, IRQ2, IRQ3, and IRQ6 interrupts can be cleared by writing a 1 to the
corresponding status bit in the register. When programmed as level-triggered interrupts,
these interrupts are cleared at the requesting sources.
SPIM—SPI Master Interrupt Request
When this bit is set, it indicates that a data transfer is complete. You must clear this interrupt
in the serial peripheral interface control register. This interrupt is a level 4 interrupt.
0 = No SPI Master interrupt pending.
1 = A SPI Master interrupt is posted.
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