
System Control
4-2
MC68328 USER’S MANUAL 12/9/97
MOTOROLA
MODULE
SYSTEM
CONTROL
4
PRELIMINARY
4.1.1 System Control Register
The 8-bit read/write system control register (SCR) resides at 0xFFF000 or 0xFFFFF000
after reset. The SCR cannot be accessed in user data space if the SO bit is set to 1. Writing
a 1 to the status bits in this register clears them, but writing a 0 has no effect.
BETO—Bus Error Time-Out
This status bit indicates whether or not a bus error timer time-out has occurred. When a bus
cycle is not terminated by the DTACK signal after 128 clock cycles have elapsed, the BETO
bit is set. However, the BETEN bit must be set for a bus error timeout to occur. This bit is
cleared by writing a 1 (writing a 0 has no effect).
0 = A bus error timer time-out did not occur.
1 = A bus error timer time-out occurs because an undecoded address space has been
accessed or because a write-protect or privilege violation has occurred.
WPV—Write-Protect Violation
This status bit indicates that a write-protect violation has occurred. If a write-protect violation
occurs and the BETEN bit is not set, the cycle will not terminate. The BETEN bit must be set
for a bus error exception to occur during a write-protect violation. This bit is cleared by
writing a 1 (writing a 0 has no effect).
0 = A write-protect violation did not occur.
1 = A write-protect violation has occurred.
PRV—Privilege Violation
This status bit indicates that If a privilege violation occurs and the BETEN bit is not set, the
cycle will not terminate. The BETEN bit must be set for a bus error exception to occur during
a privilege violation. This bit is cleared by writing a 1 (writing a 0 has no effect).
0 = A privilege violation did not occur.
1 = A privilege violation has occurred.
BETEN—Bus-Error Timeout Enable
This control bit enables the bus error timer.
0 = Disable the bus error timer.
1 = Enable the bus error timer.
SCR
BIT
7
6
5
4
3
2
1
0
FIELD
BETO
WPV
PRV
BETEN
SO
DMAP
RESERVED
WDTHB
R/W
R/W
RESET
0x0C
ADDR
0x(FF)FFF000