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Signals
2-3
MC68328 USER’S MANUAL 11/6/97
MOTOROLA
SIGNAL
DESCRIPTIONS
2
PRELIMINARY
2.1.1 Power Pins
The MC68328 processor has 20 power supply pins. Users should be careful to reduce
noise, potential crosstalk, and RF radiation from the output drivers. Inputs may be +5 V or
+3.3V when VDD = +3.3V or +5V respectively without damaging the device.
VDD (7)—7 power pins
VSS (9)—9 ground pins
PLLVDD (1)—1 power pin for the PLL
PLLVSS (1)—1 ground pin for the PLL
2.1.2 4. Clock Pins
EXTAL—EXTERNAL CLOCK/CRYSTAL INPUT
This input provides 3 clock generation options: (1) low frequency crystal, (2) low frequency
external clock, and (3) high frequency external clock. While PC0/MOCLK is low, the on-chip
phase-locked loop is enabled, creating the high-speed system clock from a low frequency
reference. EXTAL may be used (with XTAL) to connect an external crystal to the on-chip
oscillator and clock generator. If an external clock instead of a crystal is used, the clock
source should be connected to EXTAL, and XTAL left unconnected. The internal PLL
generates the system clock at 16.58 MHz from a 32.768 kHz or 38.4 kHz source. When an
external clock is used, it must provide a CMOS level at this input frequency.
While PC0/MOCLK is high, the PLL is disabled and the system clock must be connected to
the EXTAL pin. If the real-time clock is used, 32.768 kHz or 38.4 kHz must be driven into
PG7/RTCO.
XTAL—CRYSTAL OUTPUT
This output connects the on-chip oscillator output to an external crystal. If an external clock
is used, XTAL should remain unconnected.
CLKO—CLOCK OUT
This output clock signal is derived from the on-chip clock oscillator and is internally
connected to the clock output of the internal PLL. This signal is provided for external
reference. The output can be disabled to reduce power consumption.
PC0/MOCLK—Clock Mode Select, Port C I/O
While this pin is high, the MC68328 processor is in the external clock mode and the on-chip
PLL is disabled. The system clock must be driven into the EXTAL pin. While this pin is low,
it enables the PLL. Either a 32.768 kHz or 38.4 kHz clock can be driven in to the EXTAL pin,
or a crystal can be connected between EXTAL and XTAL to create an oscillator. PC0/
MOCLK can be programmed as a general-purpose I/O while the internal PLL is enabled.