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參數(shù)資料
| 型號： | MC68328PV |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 127/198頁 |
| 文件大小： | 551K |
| 代理商： | MC68328PV |
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Chip-Select Logic
MOTOROLA
MC68328 USER’S MANUAL 12/9/97
5-3
CHIP-SELECT
LOGIC
5
PRELIMINARY
5.1.1 Programmable Data Bus Size
Each chip-select can be configured to address an 8- or 16-bit space. You can mix 16- and
8-bit contiguous address memory devices on a 16-bit data bus system. If the core performs
a 16-bit data transfer in an 8-bit memory space, then two 8-bit cycles will occur. However,
the address and data strobes remain asserted until the end of the second 8-bit cycle. In this
case, only the external core data bus upper byte (D[15:8]) is used and the least-significant
bit of address (A0) increments automatically from one to the next. A0 should be ignored in
16-bit data-bus cycles even if only the upper or lower byte is being read or written. For an
external peripheral that only needs an 8-bit data bus interface and does not require
contiguous address locations (unused bytes on empty addresses), use a chip-select
configured to a 16-bit data bus width and connect to the D[7:0] pins. This balances the load
of the two data bus halves in an 8-bit system. The internal data bus is16 bits wide. All internal
registers can be read or written in one zero wait-state cycle.
Each chip-select defaults to a 16-bit data bus width. The BUSW field in the chip-select option
registers enable 16- and 8-bit data bus widths for each of the 16 chip-select ranges. You can
select the initial bus width for the boot chip-select by placing a logic 0 or 1 on the BBUSW
pin at reset to specify the width of the data bus. This allows a boot EPROM of the data bus
width to be used in any given system. All external accesses that do not match one of the
chip-select address ranges are assumed to be a 16-bit device. That is just one access
performed for a 16-bit transfer. It can also be a 8-bit port accessed every other byte.
The boot chip-select is initialized from reset to assert in response to any address except the
on-chip register space (0xXXFFF000 to 0xXXFFFFFF). This ensures that a chip-select to
the boot ROM or EPROM will fetch the reset vector and execute the initialization code, which
should set up the chip-select ranges.
A logic 0 on the BBUSW pin makes the boot device’s data bus 8 bits wide and a logic 1
makes it 16 bits wide. At reset, the data bus port size for CSA0 and the data width of the
boot ROM device are determined by the state of the BBUSW pin. The other chip-selects are
initialized to be nonvalid, so they will not assert until they are programmed and the V bit is
set.
Note: If the group address and chip-select registers are programmed to overlap, the
CSx signals will overlap too. Unused chip-selects must be programmed to 0 wait
states and 16 bits wide. Map them to dummy space if necessary. When you are
configuring the chip-select signals, the core can be set to write to a read-only
location. This causes the CS and DTACK signals to not be asserted and the
BERR signal to be asserted if a bus error timer is enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68328UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Portable System Processor-DragonBall |
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