參數(shù)資料
型號(hào): MC68328PV
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP144
封裝: PLASTIC, TQFP-144
文件頁(yè)數(shù): 171/198頁(yè)
文件大小: 551K
代理商: MC68328PV
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Parallel Ports
MOTOROLA
MC68328 USER’S MANUAL 12/9/97
7-13
PARALLEL
PORTS
7
PRELIMINARY
DIR—Direction 0–7
These bits control the directions for the associated port pin. When a bit is high, the
corresponding port pin is an output pin and when it is low the corresponding port pin is an
input pin. These bits reset to 0 and do not affect the pins while the SEL bits are low.
D—Data 0–7
These bits control or report the data on the pins. When the DIR bits are high, D[7:0] control
the data to the pins. Data can be read from or written to any bit. When the DIR bits are low,
D[7:0] report the signal level on the pins. In this case, writing to a read-only bit does not affect
the pin. Notice that the actual value on the pin is reported when a pin is read. At reset, all
data bits default to 0.
PU—Pull-Up 0–7
These bits enable the pull-up resistors on the port. When high, the pull-up resistors are
enabled and when they are low they are disabled. The port E Bit 7 pull-up resistor is enabled
after reset.
SEL—Select 0–7
The select register allows you to individually select the function for each port pin. When you
set a bit in this register, the corresponding port pin is configured as a general-purpose I/O.
When a bit is cleared, the corresponding port pin is configured as a chip-select signal.
7.5.6 Port F Registers
Port F is multiplexed with address lines A[31:24]. Depending on the system’s specification,
you can decide which of these address lines to use outside the chip. Unused address pins
can serve as parallel I/O pins.
DIR—Direction 0–7
These bits control the direction of the corresponding port pin. When a bit is high, the
corresponding port pin is an output pin and when it is low the corresponding port pin is an
input pin. These bits reset to 0 and do not affect the behavior of the pins while the SEL bits
are low.
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIELD
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
D7
D6
D5
D4
D3
D2
D1
D0
RESET
0x0000
ADDR
0xFFFFF428
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIELD
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0
RESET
0xFFFF
ADDR
0xFFFFF42A
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