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參數(shù)資料
| 型號： | MC68328PV |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 139/198頁 |
| 文件大?。?/td> | 551K |
| 代理商： | MC68328PV |
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Interrupt Controller
6-4
MC68328 USER’S MANUAL 12/9/97
MOTOROLA
MODULE
INTERRUPT
6
CONTROLLER
PRELIMINARY
6.2 RESET
The reset exception corresponds to the highest exception level. A reset exception is
processed for system initialization and to recover from a catastrophic failure. Any processing
that is in progress at the time of the reset is aborted and cannot be recovered. Neither the
program counter nor the status register is saved. The processor is forced into the supervisor
state. The interrupt priority mask is set at level 7. The address in the first 2 words of the reset
exception vector is fetched by the processor as the initial SSP (Supervisor Stack Pointer),
and the address in the next two words of the reset exception vector is fetched as the initial
program counter.
At start-up or reset, the default chip-select (CSA0) is asserted and all other chip-selects are
negated. You should use CSA0 to decode an EPROM/ROM memory space. In this case,
the first two long-words of the EPROM/ROM memory space should be programmed to
contain the initial SSP and PC. The initial SSP should point to a RAM space and the initial
PC should point to the start-up code within the EPROM/ROM space so that the processor
can execute the start-up code to bring up the system.
RESET is an input-only pin on the DragonBall. For more information about core interrupts,
see the Motorola application note called
A Discussion of Interrupts for the MC68000 (part
number AN1012).
6.3 INTERRUPT CONTROLLER
When interrupts are received by the controller, they are prioritized and the highest enabled
pending interrupt is posted to the core. Before the CPU responds to this interrupt, the status
register is copied internally. Then the S bit of the status register is set, which puts the
processor into supervisor mode. The CPU then responds with an interrupt acknowledge
cycle, in which the lower 3 bits of the address bus reflect the level of the current interrupt.
The interrupt controller generates a vector number during the interrupt acknowledge cycle
and the CPU uses this vector number to generate a vector address. Except for the reset
exception, the CPU saves the current processor status, including the program counter value
(which points to the next instruction to be executed after the interrupt), and the saved copy
of the status register. The new program counter is updated to the content of the interrupt
vector, which points to the interrupt service routine. The CPU then resumes instruction
execution to execute the interrupt service routine.
Interrupt priority is based on the interrupt level. If the CPU is currently processing an
interrupt service routine and a higher priority interrupt is posted, the process described
above repeats, and the higher priority interrupt is serviced. If the priority of the newer
interrupt is lower than or equal to the priority of the current interrupt, execution of the current
interrupt handler continues. This newer interrupt is postponed until its priority becomes the
highest. Interrupts within a same level should be prioritized in software by the interrupt
Note: The DragonBall does not support the reset instruction. It will not cause a reset
exception or an assertion of the RESET pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68328UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Portable System Processor-DragonBall |
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| MC68330CFE16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330CFE8V | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330CFG16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
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