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參數(shù)資料
| 型號： | MC68328PV |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 73/198頁 |
| 文件大小： | 551K |
| 代理商： | MC68328PV |
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Phase-Locked Loop and Power Control
MOTOROLA
MC68328 USER’S MANUAL 11/10/97
15-5
PHASE-LOCKED
LOOP
3
AND
POWER
CONTROL
PRELIMINARY
;interrupt service for Timer 2 occurs here
move.w (SP)+,IMR
;restore the Interrupt Mask Register
rts
;PLL is now at the new frequency
;The PLL has reacquired lock and SYSCLK is stable
The master frequency should only be changed during an early phase of the boot-up
sequence.
15.2.5 PLL Shutdown
The procedure for PLL shut down to place the system in sleep mode is similar to changes
made to the frequency. The difference is that the system can be awakened only by an
interrupt or reset. While there are different approaches, the simplest is to synchronize the
software to the rising edge of CLK32, write the disable bit, then execute a STOP instruction.
The CPU no longer fetches instructions then waits for the clock to stop. When an interrupt
awakens the system after the PLL acquires lock, the CPU executes an interrupt-service
routine for the level of the pending interrupt. After the interrupt-service routine, the CPU
begins execution at the instruction after the STOP instruction. The instruction sequence
below illustrates the flow. It is assumed that all peripherals and the LCD controller have been
shut down before the PLL stops.
lea #$FFF202, A1
point to the Freq Sel Register
lea #FFF200, A0
also point to PLL Control Register
WAIT
move.w (A1),D0
synchronize to rising CLK32 edge
bpl.w WAIT
wait for CLK32 to go high
bset #3,(A0)
Disable the PLL
stop #$2000
stop fetching and wait for any IRQ
* The system waits here for the PLL to restart after a wakeup IRQ
* After the IRQ routine, the instruction flow continues from here
JMP STARTUP
jump to housekeeping routine
15.3 POWER CONTROL MODULE OVERVIEW
The power control module improves power efficiency as it allocates power (clocks) to the
CPU core and other modules in the MC68328 processor under software control. Clocks can
be enabled in bursts. While executing tasks that require significant CPU resources, the clock
can be enabled for extended periods of time. While the CPU is relatively idle, the clock can
be disabled or bursted with a low duty cycle. When a wakeup interrupt occurs, the clock is
immediately enabled, allowing the CPU to service the request. The DMA controller is not
affected by the power controller. It has full access to the bus while the CPU is idle, keeping
Note: If setting the DISPLL bit does not put the MC68328 into sleep mode, it is probably
because an interrupt was asserted and was not disabled as a wake-up event in
the Interrupt Wake-Up Enable Register. An interrupt can be a wake-up event and
still be masked from causing a CPU interrupt. See Section 2.3.3.5.
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