Signals
2-4
MC68328 USER’S MANUAL 11/6/97
MOTOROLA
SIGNAL
DESCRIPTIONS
2
PRELIMINARY
2.1.3 System Control Pins
RESET
This active-low input signal causes the entire MC68328 processor (CPU and peripherals) to
enter the reset state (cold reset). Users should drive this signal low for at least 100 msec at
initial power-up to ensure that the crystal oscillator starts and stabilizes.
BBUSW—Boot Bus Width-Select
This input defines the data bus width for the boot chip-select, CSA0. BBUSW = 0 means the
boot chip-select addresses an 8-bit memory space. BBUSW=1 means the boot memory
space is 16-bits wide. Users can create a mixed 8/16 bit memory system by programming
the memory space widths in the various chip-select control registers.
2.1.4 Address Bus Pins
These are the address lines driven by the 68EC000 core or by the LCD controller for panel
refresh DMA. The chip-select module can decode the entire 4 Gbyte address map. In many
applications, only the lower portion of the address lines will be used, reserving any unused
address pins for parallel I/O functions.
A15—A0
These address output lines are not multiplexed with any other I/O signals.
PA7-PA0/A16-A23
These address lines are multiplexed with I/O port A. When programmed as I/O ports, they
serve as general-purpose I/O ports; otherwise, they are output-only address signals. These
signals default to address lines at reset where the address lines are all zeroes. Users should
note that there may be contention if any logic “1” levels are driving these pins during or after
reset.
PF7-PF0/A31-A24
These bus pins are the extended address for 68EC000 core and are multiplexed with port
F. In most systems, these lines are not used as addresses because most memory chips can
be mapped into blocks of less than 16 Mbytes. These pins default to the port F I/O function
after reset.
2.1.5 Data Bus Pins (D15–D0)
The flexible data bus interface design of the MC68328 processor allows users to program
the lower byte of the data bus in an 8-bit-only system as general-purpose I/O signals.
D15–D8
The upper byte of the data bus is not multiplexed with any other signals. In pure 8-bit
systems, this is the data bus. In mixed 8-/16-bit systems, 8-bit memory blocks or peripherals
should be connected to this bus.