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參數(shù)資料
| 型號(hào)： | MC68328PV |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 37/198頁 |
| 文件大?。?/td> | 551K |
| 代理商： | MC68328PV |
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Universal Asynchronous Receiver/Transmitter
11-4
MC68328 USER’S MANUAL 12/9/97
MOTOROLA
UART
11
PRELIMINARY
The UART module is easy to use from both a hardware and a software perspective. Five
working registers provide all of the status and control functions and they are optimized for a
16-bit bus. For example, all status bits associated with the received data are available along
with the data byte in a single 16-bit read. All register bits are readable and most are
read/write.
The modem control signals are flexible. CTS is an input that can provide hardware
flow-control to the transmitter or it can serve as a general-purpose input. A maskable
interrupt is posted on each transition of this signal. RTS is an output from the receiver that
indicates that the receiver has space in the FIFO for data. This bit can be configured as a
general-purpose output. A GPIO pin is provided that can bring an external bit-clock into the
module. It can also serve as a general-purpose input with a maskable interrupt posted on
each transition. It can be configured as an output that provides a bit clock or a signal under
software control. The UART module consists of a transmitter, a reciever, a baud rate
generator, and an MPU interface.
11.3.1 Transmitter
The transmitter accepts a character (a byte) from the MPU bus and transmits it serially.
While the FIFO is empty, the transmitter outputs continuous idle (1 in NRZ mode and 0 in
infra-red mode). When a character is available for transmission, the START, STOP, and
PARITY (if enabled) bits are added to the character and it is serially shifted at the selected
bit rate. The transmitter posts a maskable interrupt when it needs more data from the CPU.
Three interrupts are available. If you want to take full advantage of the 8-byte FIFO, the FIFO
empty interrupt should be enabled. In the interrupt service routine, the FIFO should be
interrogated after each byte is loaded. If space is available (the TX AVAIL bit is set), more
data will be loaded into the FIFO. The transmitter will not generate another interrupt until the
FIFO has completely emptied. If you have a system that has a large interrupt service
latency, use the FIFO half interrupt. In this case, the transmitter generates an interrupt when
the FIFO occupancy is less than 4 bytes. If the FIFO is not needed, use the TX avail
interrupt. An interrupt will be generated whenever at least one space is available in the FIFO.
CTS can control the serial data flow. If CTS is negated (high), the transmitter finishes
sending the character in progress (if any), then waits for CTS to again become asserted
(low) for the next transmission. Set the SEND BREAK bit in the UART transmitter register
to generate a break character (continuous 0s). Your software must know the baud rate. The
SEND BREAK bit must be asserted for a sufficient amount of time to generate a valid break
character. You can generate parity errors for debugging purposes. The transmitter operates
from the 1x clock provided by the baud rate generator.
While the infra-red interface is enabled, the transmitter produces a pulse that is 3/16 of a bit
time for each 0 bit that is sent. The TXD port directly interfaces with popular infra-red
transceivers.
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