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參數(shù)資料
| 型號(hào)： | MC68328PV |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 71/198頁(yè) |
| 文件大小： | 551K |
| 代理商： | MC68328PV |
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Phase-Locked Loop and Power Control
MOTOROLA
MC68328 USER’S MANUAL 11/10/97
15-3
PHASE-LOCKED
LOOP
3
AND
POWER
CONTROL
PRELIMINARY
15.1.2 Frequency Select Register
This register (illustrated in Figure 3-3) controls the two dividers of the dual-modulus counter.
One additional bit assists the software to protect the PLL from accidental writes that change
the frequency. Another bit prepares for the VCO frequency change. While this register can
be accessed as bytes, it should always be written as a 16-bit word.
CLK32—Clock 32
This bit indicates the current status of the CLK32 signal and synchronizes the software to
the 32kHz reference clock when the VCO frequency is to be changed or the PLL is to be
disabled. Refer to Section Section 15.2 PLL Operation for details.
PROT—Protect Bit
This bit protects the “P” and “Q” counter values from additional writes. After this bit is set by
software, the frequency-select register cannot be written. Only a reset clears this bit.
QC—Q Count
These bits control the “Q” counter.
PC—P Count
These bits control the “P” counter.
15.2 PLL OPERATION
This section describes the operation and preferred sequences to control the PLL.
15.2.1 Initial Powerup
At initial powerup, the crystal oscillator begins oscillation within several hundred
milliseconds. While reset remains asserted, the PLL begins the lockup sequence and locks
within several milliseconds of the crystal oscillator startup. Once lockup occurs, the system
clock is available at the default master frequency of 16.580608 MHz (assuming a 32.768
kHz crystal). To generate the master frequency, multiply the reference (32.768 kHz) by the
PLL divisor. The default divisor is 506. The divisor can be changed under software control
and is outlined below.
15
14
13
12
11
10
9876543210
CLK32
PROT
UNUSED
QC
PC
Address: $(FF)FFF202
Reset Value: $0123
Note: The default divider value (506) was selected as it can directly generate standard
baud frequencies at accuracies of better than 0.05%.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68328UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Portable System Processor-DragonBall |
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| MC68330CFE8V | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
| MC68330CFG16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated CPU32 Processor |
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