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參數(shù)資料
| 型號： | L64381 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 69/109頁 |
| 文件大?。?/td> | 815K |
| 代理商： | L64381 |
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Bus Interface
4-13
The L64381 may assert ABORT_OUT, due to a failing condition, during
a bus write. ABORT_OUT is deasserted only after WRITE_IN_PKT is
deasserted. Figure 4.9 shows the assertion of ABORT_OUT during a
write transfer in Port 0.
Figure 4.9
Writing Packets to
the L64381 with
ABORT_OUT
Asserted
The arbitration chip receives assertion of the BUF_AVAIL, and grants the
request by asserting the WRITE_IN_PKT and PORT_NO[1:0] signals
when it has data to write to the L64381. The source of the transfer then
drives the DATA[31:0], BYTE_VALID[3:0], SOP, and EOP signals, and the
Bus-In State Machine writes the data on the bus into the Transmit FIFO.
After the state machine writes the Bus Transfer Size number of words, it
stops writing to the FIFO.
Because the arbitration chip knows that the L64381 only drives the bus
for Bus Transfer Size cycles, it can pipeline the WRITE_IN_PKT and
PORT_NO[1:0] signals to different devices to ensure minimum latency.
Figure 4.10 shows a read transfer followed by a write, and Figure 4.11
illustrates a write transfer followed by a read. Figure 4.10 shows that at
least two cycles are needed between the deassertion of
READ_OUT_PKT and the assertion of WRITE_IN_PKT when a read is
followed by a write. This is to prevent contention for the data bus.
Figure 4.11 shows that there should be at least one cycle between the
CLOCK
BYTE_VALID[3:0]
SOP
DATA[31:0]
PORT_NO[1:0]
WRITE_IN_PKT
EOP
STROBE
BUF_AVAIL
00
2
PORT PORT PORT PORT
0
1
2
3
ABORT_OUT
0000
2
D
D
D
D
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