參數(shù)資料
型號(hào)： L64381
廠商： LSI Corporation
英文描述： 4-Port Ethernet Controller(四端口以太網(wǎng)控制器)
中文描述： 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器）
文件頁(yè)數(shù)： 36/109頁(yè)
文件大?。?/td> 815K
代理商： L64381
2-20
Registers
2.8
Receive FIFO
Head Pointer
Registers
Figures 2.20 and 2.21 show the Receive FIFO Head Pointer Registers.
These registers are used to read and write the Receive FIFO head point-
ers. The head pointers point to the first location in the Receive FIFO with
valid data to read. Register 0 contains the head pointers for Ports 0 and
1, and register 1 contains the head pointers for Ports 2 and 3. The FIFO
pointers are each five bits in length. The most-significant bits of both
bytes (bits [15:13] and [7:5]) are ignored on a write instruction, and a
read of these registers returns a zero in bits [15:13] and [7:5].
Figure 2.20
Receive FIFO Head
Pointer Register 0
Figure 2.21
Receive FIFO Head
Pointer Register 1
2.9
Receive FIFO
Tail Pointer
Registers
Figures 2.22 and 2.23 show the Receive FIFO Tail Pointer Registers.
These registers are used to read and write the Receive FIFO tail point-
ers. The tail pointers point to the first empty location in the Receive FIFO
for writing data. Register 0 contains the tail pointers for Ports 0 and 1,
and register 1 contains the tail pointers for Ports 2 and 3. The FIFO
pointers are each five bits in length. The most-significant bits of both
bytes (bits [15:13] and [7:5]) are ignored on a write instruction, and a
read of these registers returns a zero in bits [15:13] and [7:5].
15
13 12
8
7
5
4
0
Reserved
RHEAD1
Reserved
RHEAD0
15
13 12
8
7
5
4
0
Reserved
RHEAD3
Reserved
RHEAD2
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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L643F 制造商:CRYDOM 制造商全稱:Crydom Inc., 功能描述:Power Modules
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