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參數(shù)資料
| 型號： | L64381 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 64/109頁 |
| 文件大?。?/td> | 815K |
| 代理商： | L64381 |
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4-8
L64381 Operation
the SOP always occurs in the first or second word of a transfer, but the
EOP can occur anywhere within the transfer. The L64381 may assert
ABORT_OUT due to a failing condition only with the EOP during a bus
read. ABORT_OUT is asserted only for one cycle.
There should be at least one wait cycle between two consecutive bus
reads. Figure 4.4 shows two wait states asserted between reads from
Port 1 and Port 2. When the EOP signal occurs in the middle of a
transfer, the state machine drives idle data (zeros) on the DATA[31:0] out-
puts and ones on the BYTE_VALID[3:0], SOP, and EOP outputs in the
following cycles until it detects a deassertion of the READ_OUT_PKT
signal, at which time it 3-states DATA[31:0], BYTE_VALID[3:0], SOP, and
EOP. Figure 4.5 shows a bus read from Port 0 with EOP assertion in the
middle of the transfer.
Figure 4.5
Read Packet with
EOP in the Middle
of a Transfer
If the current data transfer on the bus does not contain an end of packet,
then the state machine transfers the number of words specified by the
Bus Transfer Size, and then 3-states the DATA[31:0], BYTE_VALID[3:0],
SOP, and EOP signals after the READ_OUT_PKT signal is deasserted.
This operation allows the external arbitration logic to grant the bus to
another device without having to wait for the Bus Transfer Size amount
of cycles. If the state machine detects that the READ_OUT_PKT signal
CLOCK
BYTE_VALID[3:0]
SOP
DATA[31:0]
PORT_NO[1:0]
READ_OUT_PKT
EOP
STROBE
PKT_AVAIL
PORT PORT PORT PORT
0
1
2
3
0x00000000
1111
2
0000
2
BV
1
D
D
1. Valid values for BYTE_VALID[3:0] are 0000
2
, 0001
2
, 0011
2
and
0111
00
2
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