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參數(shù)資料
| 型號： | L64381 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 38/109頁 |
| 文件大?。?/td> | 815K |
| 代理商： | L64381 |
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2-22
Registers
2.11
Transmit FIFO
Tail Pointer
Registers
Figures 2.26 and 2.27 show the Transmit FIFO Tail Pointer Registers.
These registers are used to read and write the Transmit FIFO tail point-
ers. The tail pointers point to the first empty location in the Transmit FIFO
for writing data. Register 0 contains the tail pointers for Ports 0 and 1,
and register 1 contains the tail pointers for Ports 2 and 3. The FIFO
pointers are each five bits in length. The most-significant bits of both
bytes (bits [15:13] and [7:5]) are ignored on a write instruction, and a
read of these registers returns a zero in bits [15:13] and [7:5].
Figure 2.26
Transmit FIFO Tail
Pointer Register 0
Figure 2.27
Transmit FIFO Tail
Pointer Register 1
2.12
Receive EOP
Counters
Figures 2.28 and 2.29 show the Receive EOP Counters. These counters
count the number of end of packets (EOPs) that are in the Receive FIFO.
The port increments the counter when it receives the end of a packet,
and decrements the counter when the Bus Interface asserts EOP on the
bus. If the counter value is greater than or equal to one, there is at least
one EOP in the Receive FIFO. Even if the number of bytes left in the
FIFO is less than the programmed bus transfer size (BUS field), the
L64381 still asserts PKT_AVAIL to allow the host to drain the Receive
FIFO. This scheme permits better use of the Receive FIFO, because no
padding of data is needed to align it with the Bus Transfer Size, hence
FIFO space is not wasted with pad data. Counter 0 contains the counter
values for Ports 0 and 1, and Counter 1 contains the counter values for
Ports 2 and 3.
15
13 12
8
7
5
4
0
Reserved
TTAIL1
Reserved
TTAIL0
15
13 12
8
7
5
4
0
Reserved
TTAIL3
Reserved
TTAIL2
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