參數(shù)資料
型號: L64381
廠商: LSI Corporation
英文描述: 4-Port Ethernet Controller(四端口以太網(wǎng)控制器)
中文描述: 4端口以太網(wǎng)控制器(四端口以太網(wǎng)控制器)
文件頁數(shù): 13/109頁
文件大?。?/td> 815K
代理商: L64381
Key Features
1-3
The Bus Interface is designed to allow efficient transfers of packet data
to and from the L64381. Four bytes of data can be transferred per cycle
on the bus with a burst size of 4, 8, or 16 words. One dead cycle is
required between each burst cycle.
The scan interface allows for board-level testing using the JTAG (IEEE
1149.1) standard.
LSI Logic fabricates the L64381 in the CMOS cell-based process. The
L64381 is available in a 208-pin Plastic Quad Flat Pack (PQFP) package.
1.2
Key Features
This section lists the general features of the L64381.
1.2.1
Ethernet Core
The Ethernet core features are categorized into four subsections: MAC,
Encoder/Decoder, twisted-pair transceivers, and AUI transceivers.
1.2.1.1 MAC Features
IEEE 802.3 Ethernet Standards support
Complete CSMA/CD Medium Access Control functions
Twisted-pair, full-duplex mode for 20 Mbit/s throughput
Individual address filter (individual and promiscuous addressing
modes)
Internal FCS generator and checker
1.2.1.2 Encoder/Decoder
10 Mbit/s Manchester encoding/decoding
Digital PLL with synchronous data recovery
Manchester data decoded with 18-ns jitter
PLL with fast-lock time
Elasticity:
Maximum time: 600 ns
Maximum clock error @ 1518 byte frame: 0.05%
Maximum clock error @ 4500 byte frame: 0.016%
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