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參數(shù)資料
| 型號(hào)： | L64381 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 23/109頁 |
| 文件大小： | 815K |
| 代理商： | L64381 |
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Configuration Registers
2-7
SOPCFG
Start of Packet Configuration
When this bit is set to one, the L64381 assumes that the
first word in any packet that the host writes into its Trans-
mit FIFO contains Packet Configuration Information. In
this case, the least-significant four bits in the Packet
Configuration Register are ignored and are replaced with
the four least-significant bits from the first word in the
packet. Therefore, each port is configured on a per-
packet basis. In addition, when the L64381 receives
packets from the Ethernet, it appends one extra word
containing the PORT ID number in front of the packet so
that the host knows which port the packet is coming from,
and can insert the Packet Configuration Information into
this space later. (The PORT ID number is placed at the
least-significant byte of the first word.)
4
If SOPCFG is not set, then the Packet Configuration
Information bits of the Packet Configuration Register are
used as the Packet Configuration Information for all pack-
ets that are transmitted by the L64381. In this case, the
PORT ID number is not used. Refer to Figure 4.4 for SOP
timing.
ENDN
Endian Addressing
When this bit is set to zero, the L64381 addressing mode
on the Processor Interface is big endian (see Figure 2.3).
When this bit is set to one, the addressing mode is little
endian (see Figure 2.4). Because the L64381 is not byte
addressable, this bit only affects the Burst Read
instruction.
3
Figure 2.3
Big-Endian
Addressing
Figure 2.4
Little-Endian
Addressing
PDATA15
PDATA0
Most-Significant 16 bits
first read
Least-Significant 16 bits
second read
PDATA15
PDATA0
Least-Significant 16 bits
first read
Most-Significant 16 bits
second read
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