參數(shù)資料
型號: L64381
廠商: LSI Corporation
英文描述: 4-Port Ethernet Controller(四端口以太網(wǎng)控制器)
中文描述: 4端口以太網(wǎng)控制器(四端口以太網(wǎng)控制器)
文件頁數(shù): 60/109頁
文件大?。?/td> 815K
代理商: L64381
4-4
L64381 Operation
ters,” for more information on accessing the Data FIFOs using the Data
FIFO registers.
Figure 4.2
Data FIFO Block
Diagram
4.2.1
Transmit FIFO
The Transmit FIFO can be configured to store the first 64 bytes of a
packet until the first 64 bytes have been successfully transmitted. This
allows the chip to retransmit the packet without requiring a bus access
when a collision occurs in the first 51.2
μ
s. Once the first 64 bytes have
been successfully transmitted, the FIFO releases the first 64 bytes, thus
allowing utilization of the whole FIFO for storage.
The Transmit FIFO also allows storage of succeeding packets to be
transmitted while the previous packet is still being transmitted. This fea-
ture allows back-to-back transmissions of packets without any wasted
bandwidth on the Ethernet, and also allows better usage of the FIFO.
If a late collision occurs in the transmission of a packet, then the chip
generates an interrupt and updates the appropriate Statistics Counters.
The Processor can then read the error register, and decide on the
appropriate action. If another packet is available for transmission in the
4 bits
4 Words
3
36 bits
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