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參數(shù)資料
| 型號： | L64381 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 59/109頁 |
| 文件大?。?/td> | 815K |
| 代理商： | L64381 |
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On-chip FIFOs
4-3
systems integration building block for developing next-generation
networking products for switched hub or router applications. The core
also enables the highest form of system integration for workstation or
high-end PCs by converting all the I/O and system logic into a single-
chip solution.
The functional blocks within the core are:
Manchester Encoder/Decoder. The core contains an integrated
Encoder/Decoder function that performs Manchester encoding and
decoding, and utilizes a digital phase-locked loop for data recovery
at 10 Mbit/s.
Media Access Control (MAC). The Media Access Control function
provides simple and efficient packet transmission and reception
control by means of parallel eight-bit data interfaces.
Transceiver Interface. The core provides inputs and outputs that are
easily connected to on-chip integrated 10BASE-T (twisted-pair)
transceivers compatible with IEEE 802.3 networks. The core can
also provide AUI signals for 10BASE-2, 10BASE-5, or 10BASE-F
media. The core may be connected directly to the MAC interface.
The transceiver interface logic incorporates the transmitter, receiver,
collision, link integrity, and loopback functions as defined in the
standard.
4.2
On-chip FIFOs
Each Ethernet port in the L64381 contains a 128-byte Transmit FIFO and
a 128-byte Receive FIFO. Each location addresses a word (four bytes)
of data, along with the four encoded value bits. The FIFO also maintains
the Start-of-Packet and End-of-Packet information, which makes the
actual FIFO structure 32 x 36 bits. FIFO pointers are maintained in
registers on the L64381. The FIFO access circuit is designed in a way
that allows FIFO reads and writes from the Ethernet ports and from the
Bus Interface to happen without conflicts or delays.
Figure 4.2 shows the 128-byte FIFO configuration. The lower 32 bits
(four words) are data; the most-significant four bits are user-encoded
values for BYTE_VALID[3:0], SOP, EOP, and AI_FCS_IN when a bus
interface transaction occurs. The RRAM and WRAM fields in the Data
FIFO Address Register correspond to the upper four bits in the FIFO for
reads and writes, respectively. Refer to Section 2.7, “Data FIFO Regis-
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