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參數(shù)資料
| 型號： | L64381 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 34/109頁 |
| 文件大?。?/td> | 815K |
| 代理商： | L64381 |
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2-18
Registers
Figure 2.15
Data FIFO Address
Register
RRAM
Read Data FIFO
During a Data FIFO read, the L64381 writes the value of
the four most-significant bits in the selected Data FIFO
location into these four bits. This value is the user-
encoded value of BYTE_VALID[3:0], SOP, EOP, and
AI_FCS_IN. The addition of this field allows reading of all
36 bits of the selected Data FIFO without requiring an
additional register decode.
[15:12]
WRAM
Write Data FIFO
These bits contain the value to be written into the upper
four bits of one of the 32 words in the selected Data
FIFO. When a bus interface transaction occurs, this value
is a user-encoded value for BYTE_VALID[3:0], SOP, EOP,
and AI_FCS_IN. The addition of this field allows writing
of all 36 bits of the Data FIFO without requiring an addi-
tional register decode.
[11:8]
FIFOS
FIFO Select
This bit selects either the Transmit FIFO (FIFOS = 0) or
the Receive FIFO (FIFOS = 1) for the read or write
operation.
7
PORTNO
Port Number
This field selects the port number (3:0) for the read or the
write operation.
[6:5]
WORDADDR
Word Address
This field selects one of the words within the 128-byte
FIFO.
[4:0]
When the processor writes to the Data FIFO Address Register, all 16 bits
of the register are written, allowing for testing of the register. If the
processor executes a Read Data FIFO instruction, the highest four bits
are overwritten with the encoded value field of the Data FIFO. Therefore,
when testing the Data FIFO Address Register, the user should execute
a Read Data FIFO Address Register instruction before executing a Read
Data FIFO instruction.
15
12 11
8
7
6
5
4
0
RRAM
WRAM
FIFOS
PORTNO
WORDADDR
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