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參數(shù)資料
| 型號： | L64381 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 11/109頁 |
| 文件大?。?/td> | 815K |
| 代理商： | L64381 |
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1-1
Chapter 1
Introduction
This document describes the L64381 (Quad CASCADE) 4-Port Ethernet
Controller device, a highly integrated CMOS solution for Local Area Net-
work (LAN) applications. The L64381 is derived from the 10-Mbps Ether-
net Controller core. This multiport solution allows system designers to
build cost-effective switched Ethernet hub or router products.
The L64381 consists of four ports, each with separate 128-byte Transmit
and Receive FIFOs. The device architecture includes a high-performance
1-Gbps bus interface designed for fast packet transfers, and a processor
interface for control and status checking purposes. The L64381 can be
programmed for full-duplex or half-duplex operation, has individual, and
promiscuous addressing modes, and supports both twisted-pair and AUI
(Attachment Unit Interface) interfaces.
The L64381 has met all IEEE 802.3 signal conformance and interopera-
bility tests.
Chapter 1 provides an overview of the L64381. It contains two sections:
Section 1.1, “Overview”
Section 1.2, “Key Features”
1.1
Overview
Figure 1.1 shows a block diagram of the L64381 device. The four Ether-
net controllers are fully independent. Each L64381 port has its own MAC
(Medium Access Control), Manchester Encoder/Decoder, and twisted-
pair/AUI transceivers. The device is fully synchronous. It operates on a
16-MHz to 33-MHz host clock and a 20-MHz network clock. The
128-byte FIFOs are configurable for optimizing latency and throughput.
Each port has 23 Statistical Counters, which provide on-chip
maintenance. These counters meet the statistics requirements of the
Simple Network Management Protocol (SNMP).
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