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參數(shù)資料
| 型號： | L64381 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 52/109頁 |
| 文件大?。?/td> | 815K |
| 代理商： | L64381 |
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3-12
Signal Descriptions
3.3
Processor
Interface
Signals
This section describes the signals that comprise the L64381’s Processor
Interface.
ADRS[5:0]
Register Select Address
These pins determine which L64381 register to access.
ADRS[5:0] are latched into the L64381 on the rising sys-
tem clock edge (CLOCK) immediately following the
assertion of ADRS_STROBE and CHIP_SELECT.
Input
ADRS_STROBE
Address Strobe
Assertion of ADRS_STROBE along with the assertion of
CHIP_SELECT causes the L64381 to latch the ADRS
inputs.
Input
CHIP_SELECT Chip Select
Input
Assertion of this input enables access to and from the
L64381 from the Processor Interface. For an absolute
worst-case condition, all the statistics counters need to
be updated when the host tries to access one of them.
The access time from ADRS_STROBE to PREADY may
be 100+ cycles. For applications with multiple L64381
devices sharing the same processor interface, when such
a worst-case condition occurs, you can deassert a partic-
ular L64381 chip select, which terminates the current
transaction and allows other devices to use the bus, if
desired.
INTERRUPT
Interrupt
The L64381 asserts INTERRUPT whenever an error bit
in the Error Register is set and that bit has not been
masked. The interrupt generally indicates any condition
which the processor needs to resolve.
Output
PDATA[15:0]
Processor Data Bus
This 16-bit bus contains data that is transferred between
the L64381 and the processor.
Bidirectional
PREADY
Ready
During a write to the L64381’s registers, the L64381
asserts PREADY LOW for one cycle after the rising edge
on which the PDATA data is latched. For a read instruc-
tion, the L64381 drives PREADY LOW for one cycle after
it places data on the PDATA bus. Data is to be read on
Output
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