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參數(shù)資料
| 型號： | L64381 |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Ethernet Controller(四端口以太網(wǎng)控制器) |
| 中文描述： | 4端口以太網(wǎng)控制器（四端口以太網(wǎng)控制器） |
| 文件頁數(shù)： | 62/109頁 |
| 文件大?。?/td> | 815K |
| 代理商： | L64381 |
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4-6
L64381 Operation
4.3
Bus Interface
The L64381 Bus Interface is comprised of two state machines: Bus Out
and Bus In. This section describes both state machines in detail.
4.3.1
Bus-Out State
Machine
The Bus Interface has four Bus-Out State Machines, one for each Ether-
net port. Each Bus-Out State Machine is responsible for transferring data
received on the port to other devices via the Bus Interface. When a word
of data has been received from the Ethernet, the L64381 places it into
the Receive FIFO. When the FIFO contains as many words as specified
in the Bus Transfer Size field of Configuration Register 1 (or if the FIFO
contains an EOP), the Bus-Out State Machine asserts the appropriate
PKT_AVAIL_PORTx signal, where x equals the port number (0 to 3).
The PKT_AVAIL_PORTx signals from the four on-chip Ethernet ports are
multiplexed on the PKT_AVAIL signal on the device pins. The multiplex-
ing is done with respect to the STROBE input. When the L64381
receives the assertion of the STROBE input, it places the states of the
PKT_AVAIL_PORTx signals onto the device pin in the following four
cycles, with PORT 0 placed first, and PORT 3 placed last. Figure 4.3
shows the timing relationship between these signals.
Figure 4.3
STROBE to
PKT_AVAIL Timing
Relationship
When the Bus-Out State Machine receives assertion of the
READ_OUT_PKT signal with the corresponding port number on the
PORT_NO[1:0] inputs, it starts sending data on to the DATA[31:0],
BYTE_VALID[3:0], SOP, and EOP outputs in the following cycle. The
L64381 drives these output signals in the cycle following detection of the
READ_OUT_PKT signal assertion. The external device will be unable to
latch the data on the third cycle. Refer to the functional waveforms for
the cycle count between signal transitions when such conflict occurs.
The state machine fetches data from the head of the Receive FIFO, and
transfers the number of words specified in the Bus Transfer Size field.
Figure 4.4 shows the details of the handshaking during a bus read.
STROBE
PORT 0
PKT_AVAIL
PORT 1 PORT 2 PORT 3
CLOCK
BUF_AVAIL
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