參數(shù)資料
型號(hào): L64381
廠商: LSI Corporation
英文描述: 4-Port Ethernet Controller(四端口以太網(wǎng)控制器)
中文描述: 4端口以太網(wǎng)控制器(四端口以太網(wǎng)控制器)
文件頁(yè)數(shù): 24/109頁(yè)
文件大小: 815K
代理商: L64381
2-8
Registers
When accessing statistics from the Statistics Counters in
big-endian and burst modes, the two most-significant
bytes of the counter are placed on the PDATA bus before
the two least-significant bytes. In little-endian and burst
modes, the two least-significant bytes are placed on the
PDATA bus before the two most-significant bytes.
The ENDN bit setting affects only the Processor Interface
and has no effect on the little-endian Bus Interface. Dur-
ing a Bus Interface write transaction, the L64381 looks for
the first valid byte from either DATA[7:0], DATA[15:8],
DATA[23:16] or DATA[31:24]. This choice depends on the
value of BYTE_VALID[3:0]. The L64381 then sends the
valid byte to the network. In the first example below,
DATA[7:0] goes to the network first, then DATA[15:8], and
finally DATA[23:16]. The second example has only two
valid bytes, so DATA[23:16] is passed to the network first,
and DATA[31:24] follows.
BURST
Burst Mode Size
These bits define the number of burst transfers that the
L64381 can perform on the Processor Interface in
response to a burst mode instruction. The Burst Mode
allows the processor to quickly read all the statistics
collected by the L64381 per Ethernet port without having
to execute individual read instructions per statistic.
[2:1]
Note :
These bits refer only to the Processor Interface;
the Bus Transfer Size (BUS) bits define the
transfer size on the Bus Interface.
BYTE_VALID[3:0]
1000
2
Invalid Byte
Third Byte
Second Byte
First Byte
0011
2
Second Byte
First Byte
Invalid Byte
Invalid Byte
BIts[31:24]
Bits [23:16]
Bits [15:8]
Bits [7:0]
BURST[2:1]
Transfer Size
00
01
10
11
2 16-bit transfers
4 16-bit transfers
8 16-bit transfers
16 16-bit transfers
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